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參數(shù)資料
| 型號(hào)： | AD7886JD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADC |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 400K |
| 代理商： | AD7886JD |
AD7886
–7–
REV. B
OFFSET AND GAIN ADJUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can usually be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as
the input signal is within the full dynamic range of the ADC.
For applications requiring that the input signal range match the
full analog input dynamic range of the ADC, offset and full-
scale errors must be adjusted to zero.
UNIPOLAR OFFSET AND GAIN ERROR ADJUSTMENT
If absolute accuracy is an application requirement, offset and
gain can be adjusted to zero. Offset error must be adjusted be-
fore gain error. Zero offset is achieved by adjusting the offset of
the op amp driving the analog input (i.e., A1 in Figure 6). For
zero offset error, apply a voltage of 1 LSB to AIN and adjust
the op amp offset until the ADC output code flickers between
0000 0000 0000 and 0000 0000 0001.
0 V to 5 V Range:
1 LSB = 1.22 mV
0 V to 10 V Range: 1 LSB = 2.44 mV
For zero gain, error apply an analog input voltage equal to
FS–1 LSB (last code transition) at AIN and adjust R3 until the
ADC output code flickers between 1111 1111 1110 and 1111
1111 1111.
0 V to 5 V Range:
FS–1 LSB = 4.99878 V
0 V to 10 V Range: FS–1 LSB = 9.99756 V
AD7886*
SUM
+
–
AD586
V
OUT
+V
IN
GND
+V
C1
10
μ
F
C2
0.1
μ
F
AD707
VIN1
VIN2**
AGND
V
SS
V
DD
AIN
R1
82k
R2
56k
R3
5k
0 TO 5V
OR
0 TO 10V
–
+
AD845
A1
5V
+
5REF
+
5V
+
3.5V
–
V
REF
5V
–
*ADDITIONAL PINS OMITTED FOR CLARITY
**0 TO 5V RANGE: CONNECT VIN2 TO VIN1
0 TO 10V RANGE: CONNECT VIN2 TO AGND
Figure 6. Unipolar Operation with Gain Error Adjust
BIPOLAR OPERATION
Bipolar operation is achieved by providing a +10 V span on
the VIN1 input while offsetting the VIN2 input by +5 V. A
typical circuit is shown in Figure 7. The output code is off-
set binary. The ideal input/output transfer characteristic is
shown in Figure 8. The LSB size is (10/4096) V = 2.44 mV.
AD7886*
SUM
+
–
AD586
V
OUT
+V
IN
GND
+V
C1
10
μ
F
C2
0.1
μ
F
AD707
VIN1
VIN2
AGND
V
SS
V
DD
AIN
*ADDITIONAL PINS OMITTED FOR CLARITY
5V
+
5REF
+
V
REF
5V
±
5V
+
5V
–
3.5V
–
Figure 7. Bipolar Operation
00...000
00...001
01...101
01...110
11...111
11...110
11...101
10...000
10...001
10...010
01...111
FS = 10V
1LSB =
FS
4096
VIN, INPUT VOLTAGE – LSBs
OUTPUT
CODE
1LSB
–
+1LSB
– 1LSB
2
FS
+
2
FS
–
+1LSB
Figure 8. Ideal Input/Output Characteristics for
Bipolar Operation
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