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參數資料
| 型號： | AD7886JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 12-Bit, 750 kHz/1 MHz, Sampling ADC |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 2/16頁 |
| 文件大?。?/td> | 400K |
| 代理商： | AD7886JP |
AD7886–SPECIFICATIONS
as shown in Figure 2. All Specifications T
MIN
to T
MAX
unless otherwise noted. Specifications apply for 750 kHz version.)
–2–
REV. B
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, A6ND = DGND = O V, V
REF
= –3.5 V, connected
Parameter
J Version
1
K, B Versions
1
T Version
1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio
3
(SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
65
–75
–77
67
–75
–77
65
–75
–77
dB min
dB typ
dB typ
VIN = 100 kHz Sine Wave, f
SAMPLE
= 750 kHz
VIN = 100 kHz Sine Wave, f
SAMPLE
= 750 kHz
VIN = 100 kHz Sine Wave, f
SAMPLE
= 750 kHz
–80
–80
–80
–80
–80
–80
dB typ
dB typ
f
a
= 96 kHz, f
b
= 103 kHz, f
SAMPLE
= 750 kHz
ACCURACY
Resolution
Integral Linearity T
MIN
to T
MAX
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Unipolar Offset Error @ +25
°
C
T
MIN
to T
MAX
Bipolar Offset Error @ +25
°
C
T
MIN
to T
MAX
Unipolar Gain Error @ +25
°
C
T
MIN
to T
MAX
Bipolar Gain Error @ +25
°
C
T
MIN
to T
MAX
12
12
±
2
12
±
2
Bits
LSB max
12
±
5
±
5
±
5
±
5
±
5
±
5
±
5
±
5
12
±
5
±
5
±
5
±
5
±
5
±
5
±
5
+5
12
±
5
±
5
±
5
±
5
±
5
±
5
±
5
±
5
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Input Range: 0 V to 5 V or 0 V to 10 V
Input Range:
±
5 V
Input Range: 0 V to 5 V or 0 V to 10 V
Input Range:
±
5 V
ANALOG INPUT
Unipolar Input Current
Bipolar Input Current
1.5
±
0.75
1.5
±
0.75
1.5
±
0.75
mA max
mA max
Input Ranges: 0 V to 5 V or 0 V to 10 V
Input Range:
±
5 V
REFERENCE INPUT
V
REF
Input Reference Current
R1, Resistance
R2, Resistance
R2/R1 Ratio
–3.5
–10
9
6.3
0.7
–3.5
–10
9
6.3
0.7
–3.5
–10
9
6.3
0.7
Volts
mA max
k
nom
k
nom
nom
±
2% For Specified Performance
±
25%
±
25%
±
0.1%
POWER SUPPLY REJECTION
V
DD
Only, (FS Change)
V
SS
Only, (FS Change)
0.5
0.5
0.5
0.5
0.5
0.5
LSB typ
LSB typ
V
SS
= –5 V, V
DD
= +4.75 V to +5.25 V
V
DD
= +5 V, V
SS
= –4.75 V to –5.25 V
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
2.4
0.8
±
10
10
2.4
0.8
±
10
10
2.4
0.8
±
10
10
V min
V max
μ
A max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
V
IN
= 0 V to V
DD
LOGIC OUTPUTS
DB11–DB0,
BUSY
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB11–DB0
Floating-State Leakage Current
Floating-State Output Capacitance
4
4
0.4
4
0.4
4
0.4
V min
V max
I
SOURCE
= 200
μ
A
I
SINK
= 1.6 mA
±
10
15
±
10
15
±
10
15
pA max
pF max
POWER REQUIREMENTS
V
DD
V
SS
I
DD
I
SS
Power Dissipation
+5
–5
35
–35
250
350
+5
–5
35
–35
250
350
+5
–5
35
–35
250
350
V nom
V nom
mA max
mA max
mW typ
mW max
±
5% for Specified Performance
±
5% for Specified Performance
Typically 25 mA,
CONVST
=
CS
=
RD
= V
DD
Typically 25 mA,
CONVST
=
CS
=
RD
= V
DD
CONVST
=
CS
=
RD
= V
DD
NOTES
I
Temperature ranges are as follows: J, K Versions: 0
°
C to +70
°
C; B Version: –40
°
C to +85
°
C; T Version: –55
°
C to + 125
°
C.
2
Applies to all three input ranges, V
= 0 to FS, pk-to-pk V.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25
°
C to ensure compliance.
Specifications subject to change without notice.
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