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參數資料
| 型號： | AD7887AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | 0.150 INCH, MS-012AA, SOIC-8 |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 133K |
| 代理商： | AD7887AR |
REV. B
AD7887
–11–
MODE S OF OPE RAT ION
T he AD7887 has a number of different modes of operation.
T hese are designed to provide flexible power management op-
tions. T hese options can be chosen to optimize the power dissi-
pation/throughput rate ratio for differing application requirements.
T he modes of operation are controlled by the PM1 and PM0 bits
of the Control Register as previously outlined. For read-only
operation of the AD7887, the default mode of all 0s in the Con-
trol Register can be set up by tying the DIN line permanently
low.
Mode 1 (PM1 = 0, PM0 = 0)
T his mode allows the user to control the powering down of the
part via the
CS
pin. Whenever
CS
is low, the AD7887 is fully
powered up; whenever
CS
is high, the AD7887 is in full shut-
down. When
CS
goes from high to low, all on-chip circuitry
starts to power up. It takes approximately, 5
μ
s for the AD7887
internal circuitry to be fully powered up. As a result, a conver-
sion (or sample-and-hold acquisition) should not be initiated
during this 5
μ
s.
Figure 13 shows a general diagram of the operation of the AD7887
in this mode. T he input signal is sampled on the second rising
edge of SCLK following the
CS
falling edge. T he user should
ensure that 5
μ
s elapses between the falling edge of
CS
and the
second rising edge of SCLK . In microcontroller applications,
this is readily achievable by driving the
CS
input from one of the
port lines and ensuring that the serial data read (from the micro-
controllers serial port) is not initiated for 5
μ
s. In DSP applica-
tions, where the
CS
is generally derived from the serial frame
synchronization line, it is usually not possible to separate the
CS
falling edge and second SCLK rising edge by up to 5
μ
s without
affecting the speed of the rest of the serial clock. T herefore, the
user will need to write to the Control Register to exit this mode
and (by writing PM1 = 0 and PM0 = 1) put the part into Mode
2, i.e., normal mode. A second conversion will then need to be
initiated when the part is powered-up to get a conversion result.
T he write operation which takes place in conjunction with this
second conversion can put the part back into Mode 1 and the
part will go into power-down mode when
CS
returns high.
Mode 2 (PM1 = 0, PM0 = 1)
In this mode of operation, the AD7887 remains fully powered
up regardless of the status of the
CS
line. It is intended for
fastest throughput rate performance as the user does not have to
worry about the 5
μ
s power-up time previously mentioned.
Figure 14 shows the general diagram of the operation of the
AD7887 in this mode.
T he data presented to the AD7887 on the DIN line during the
first eight clock cycles of the data transfer are loaded to the
Control Register. T o continue to operate in this mode, the user
must ensure that PM1 is loaded with 0 and PM0 is loaded with
1 on every data transfer.
T he falling edge of
CS
initiates the sequence and the input
signal is sampled on the second rising edge of the SCLK input.
Sixteen serial clock cycles are required to complete the conver-
sion and access the conversion result. Once a data transfer is
complete (
CS
has returned high), another conversion can be
initiated immediately by bringing
CS
low again.
SCLK
CS
DOUT
DIN
1
16
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
THE PART POWERS UP ON
CS
FALLING EDGE AS PM1 AND PM0 = 0
THE PART POWERS DOWN ON
CS
RISING EDGE AS PM1 AND PM0 = 0
Figure 13. Mode 1 Operation
SCLK
CS
DOUT
DIN
THE PART REMAINS POWERED UP
AT ALL TIMES AS
PM1 = 0 AND PM0 = 1
1
16
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
Figure 14. Mode 2 Operation
相關PDF資料 |
PDF描述 |
|---|---|
| AD7887ARM | +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC |
| AD7887BR | +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC |
| AD7888(中文) | 2.7 V to 5.25 V, Micro Power, 8-Channel,125kSPS,12-Bit ADC(微功耗,125kSPS,8通道12位A/D轉換器) |
| AD7888 | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
| AD7888AR | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7887ARM | 功能描述:IC ADC 12BIT 2CH SRL 8-MSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:16 采樣率（每秒）:45k 數據接口:串行 轉換器數目:2 功率耗散（最大）:315mW 電壓電源:模擬和數字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數目和類型:2 個單端，單極 |
| AD7887ARM-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 125ksps 12-bit Serial 8-Pin MSOP T/R |
| AD7887ARM-REEL7 | 功能描述:IC ADC 12BIT 2CH SRL 8-MSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:16 采樣率（每秒）:45k 數據接口:串行 轉換器數目:2 功率耗散（最大）:315mW 電壓電源:模擬和數字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數目和類型:2 個單端，單極 |
| AD7887ARMZ | 功能描述:IC ADC 12BIT 2CH SRL 8MSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7887ARMZ | 制造商:Analog Devices 功能描述:IC ADC 12BIT 125KSPS MSOP-8 |
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