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參數(shù)資料
| 型號(hào)： | AD7888ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | +2.7 V to +5.25 V, Micropower, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Lead TSSOP |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 164K |
| 代理商： | AD7888ARU |
REV. 0
–2–
AD7888–SPECIFICATIONS
(V
DD
= +2.7 V to +5.25 V, REFIN/REFOUT = +2.5 V External/Internal Reference unless
otherwise noted; f
SCLK
= 2 MHz (V
DD
= +2.7 V to +5.25 V); T
A
= T
MIN
to T
MAX
, unless otherwise noted)
Parameter
A Version
1
B Version
1
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio
2, 3
(SNR)
Total Harmonic Distortion
2
(THD)
Peak Harmonic or Spurious Noise
2
Intermodulation Distortion
2
(IMD)
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation
2
Full Power Bandwidth
71
–80
–80
71
–80
–80
dB typ
dB typ
dB typ
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
–78
–78
–80
2.5
–78
–78
–80
2.5
dB typ
dB typ
dB typ
MHz typ
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
f
IN
= 25 kHz
@ 3 dB
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Any Channel
12
±
2
±
2
12
±
1
±
1
Bits
LSB max
LSB max
Guaranteed No Missed Codes to 11 Bits (A Grade)
Guaranteed No Missed Codes to 12 Bits (B Grade)
V
DD
= 4.75 V to 5.25 V (Typically
±
3 LSB)
V
DD
= 2.7 V to 3.6 V (Typically
±
2 LSB)
Offset Error
±
6
±
4.5
2
±
2
2
±
6
±
4.5
2
±
2
2
LSB max
LSB max
LSB typ
LSB max
LSB max
Offset Error Match
2
Gain Error
2
Gain Error Match
2
Typically 30 LSB with Internal Reference
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
0 to V
REF
±
1
38
4
0 to V
REF
±
1
38
4
Volts
μ
A max
pF typ
pF typ
When in Track
When in Hold
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
Input Impedance
REFOUT Output Voltage
REFOUT Tempco
2.5/V
DD
5
2.45/2.55
±
50
2.5/V
DD
5
2.45/2.55
±
50
V min/max
k
typ
V min/max
ppm/
°
C typ
Functional from 1.2 V
Very High Impedance If Internal Reference Disabled
LOGIC INPUTS
Input High Voltage, V
INH
2.4
2.1
0.8
±
10
10
2.4
2.1
0.8
±
10
10
V min
V min
V max
μ
A max
pF max
V
DD
= +4.75 V to +5.25 V
V
DD
= +2.7 V to +3.6 V
V
DD
= +2.7 V to +5.25 V
Typically 10 nA, V
IN
= 0 V or V
DD
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
I
SOURCE
= 200
μ
A
V
DD
= +2.7 V to +5.25 V
I
SINK
= 200
μ
A
V
DD
–
0.5
0.4
±
10
10
Straight (Natural) Binary
V
DD
–
0.5
0.4
±
10
10
V min
V max
μ
A max
pF max
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
CONVERSION RATE
Throughput Time
16
16
SCLK Cycles
Conversion Time + Acquisition Time. 125 kSPS with
2 MHz Clock
Track/Hold Acquisition Time
2
Conversion Time
1.5
14.5
1.5
14.5
SCLK Cycles
SCLK Cycles
7.25
μ
s (2 MHz Clock)
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