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參數(shù)資料
型號: AD7889
廠商: Analog Devices, Inc.
英文描述: 12-Bit 600 kSPS ADC(單電源600kSPS12位A/D轉換器)
中文描述: 12位600 ksps模數(shù)轉換器(單電源600kSPS12位的A / D轉換器)
文件頁數(shù): 10/12頁
文件大小: 285K
代理商: AD7889
AD7889
MODE D Description.
The AD7889 can be used in Mode D by connecting
CONTCLK and 16/14B to logic 1. In this mode the AD7889
expects a continuous SCLK to be provided.The conversion is
initiated by pulsing
CONVST.
The first rising edge of the
SCLK following the
CONVST
causes the
RFS
to be as-
serted. The conversion result is available on the next 16
falling edges of SCLK (assuming IDLEHI = 1). The
RFS
returns back high on the rising edge following the
last bit of data.
10
REV. B PRELIM. 7/97
Preliminary Technical Information
Analog Input Section
The AD7889 is offered as three part types allowing for five
different analog input voltage ranges. The AD7889-1
handles either ±5V or ±10V input voltage ranges. The
AD7889-2 handles either 0 V to +2.5V or 0 V to +5 V input
voltage ranges while the AD7889-3 handles an input range of
±2.5V.
AD7889-1
Figure 3 shows the analog input section for the AD7889-1.
The analog input range is pin-strappable (using V
IN2
) for either
±5V or ±10V on the V
IN1
input. With V
IN2
connected to
AGND, the input range on V
IN1
is ±10V, and the input resis-
tance on V
IN1
is 25 k
nominal. With V
IN2
connected to V
IN1
,
the input range on V
IN1
is ±5V, and the input resistance on
V
IN1
is 15k
nominal. As a result, the V
IN1
and V
IN2
inputs
should be driven from a low impedance source. The resistor at-
tenuator stage is followed by the high input impedance stage of
the track/hold amplifier. This resistor attenuator stage allows
the input voltage to go to ±17 V without damaging the
AD7889-1.
Table II. Ideal Input/Output Code Table for the AD7889-1
Digital Output
Code Transition
Analog Input
+FSR/2 3/2 LSB
1, 2
(9.99268 or 4.99634)
3
+FSR/2 5/2 LSBs (9.98779 or 4.99390)
+FSR/2 7/2 LSBs (9.98291 or 4.99146)
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
AGND + 3/2 LSB (0.00732 or 0.00366)
AGND + 1/2 LSB (0.00244 or 0.00122)
AGND 1/2 LSB (0.00244 or 0.00122)
AGND 3/2 LSB (0.00732 or 0.00366)
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
FSR/2 + 5/2 LSB (9.98779 or 4.99390)
FSR/2 + 3/2 LSB (9.99268 or 4.99634)
FSR/2 + 1/2 LSB (9.99756 or 4.99878)
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
NOTES
1
FSR is full-scale range and VREF = +2.5 V, is 20 V for the ±10 V range and 10 V for
the ±5 V range.
2
1 LSB = FSR/4096 = 4.88 mV (±10 V range) and 2.44 mV (±5 V range) with VREF
= +2.5 V.
3
±10 V range or ±5 V range.
+2.5
REFERENCE
VREF
V
IN1
V
IN2
AGND
TO HIGH
IMPEDANCE
SHA INPUT
TO ADC
REFERENCE
CIRCUITRY
2k
5.5k
22k
11k
22k
AD7889-2
Figure 4 shows the analog input section for the AD7889-2.
The analog input range is pin-strappable (using V
IN2
) for either
0 V to +2.5 V or 0V to +5 V. With V
IN2
connected to AGND,
the input range on V
IN1
is 0 V to +5 V, and the input resistance
on V
IN1
is 11k
nominal. With V
IN2
connected to V
IN1
, the
input range on V
IN1
is 0 V to 2.5 V, and the input resistance on
V
IN1
is 2.75k
nominal. As a result, the V
IN1
and V
IN2
inputs
should be driven from a low impedance source. The resistor
attenuator stage is followed by the high input impedance stage
of the track/hold amplifier. This resistor attenuator stage
allows the input voltage to go to +7 V without damaging the
AD7889-2.
Figure 3. AD7889-1 Analog Input Structure
The designed code transitions occur midway between succes-
sive integer LSB values (i.e., 1/2LSB, 3/2LSBs, 5/2 LSBs).
Output coding is 2s complement binary with 1LSB = FSR/
4096 = 20V/4096 = 4.88mV for the ±10V range and
1LSB = FSR/4096 = 10V/4096 = 2.44mV for the ±5V
range. The ideal input/output transfer function for the
AD7889-1 is shown in Table II.
Figure 4. AD7889-2 Analog Input Structure
Once again, the designed code transitions occur midway be-
tween successive integer LSB values (i.e., 1/2LSB, 3/2LSBs,
5/2 LSBs). Output coding is straight (natural) binary with
1LSB = FSR/4096 = 2.5V/4096 = 0.61mV, for the 0 V to
2.5V range and 1LSB = FSR/4096 = 5V/4096 = 1.22mV,
for the 0 V to 5V range. The ideal input/output transfer func-
tion for the AD7889-2 is shown in Table III.
+2.5
REFERENCE
VREF
V
IN1
V
IN2
TO HIGH
IMPEDANCE
SHA INPUT
TO ADC
REFERENCE
CIRCUITRY
2k
5.5k
5.5k
AGND
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