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參數(shù)資料
型號: AD7889
廠商: Analog Devices, Inc.
英文描述: 12-Bit 600 kSPS ADC(單電源600kSPS12位A/D轉換器)
中文描述: 12位600 ksps模數(shù)轉換器(單電源600kSPS12位的A / D轉換器)
文件頁數(shù): 11/12頁
文件大小: 285K
代理商: AD7889
AD7889
REV. B PRELIM. 7/97
11
Preliminary Technical Information
+FSR 5/2 LSBs (2.498474V)
+FSR 7/2 LSBs (2.497864 V)
111 . . . 110 to 111 . . . 110
111 . . . 100 to 111 . . . 101
AGND + 5/2 LSB (0.001526V)
AGND + 3/2 LSB (0.00916V)
AGND + 1/2 LSB (0.000305V)
000 . . . 010 to 010 . . . 011
000 . . . 001 to 001 . . . 010
000 . . . 000 to 000 . . . 001
NOTES
1
FSR is full-scale range and is 5V with VREF = +2.5V.
2
1LSB = FSR/4096 = 1.22mV (0V to +5V range) and 0.61 mV (0V to 2.5V range)
with VREF = +2.5 V.
3
FSR is full-scale range and is 2.5V with VREF= +2.5 V.
AD7889-3
Figure 5 shows the analog input section for the AD7889-3.
The analog input range is ±2.5V on the V
IN1
input. The V
IN2
input can be left unconnected but if it is connected to a poten-
tial then that potential must be AGND. The input resistance
on the V
IN1
is 2.75 k
nominal. As a result, the V
IN1
input
should be driven from a low impedance source. The resistor at-
tenuator stage is followed by the high input impedance stage of
the track/hold amplifier. This resistor attenuator stage allows
the input voltage to go to ±7 V without damaging the
AD7889-3.
Figure 6. AD7889 to ADSP-21XX Interface
Table III. Ideal Input/Output Code Table for the AD7889-2
Digital Output
Code Transition
Analog Input
+FSR 3/2 LSB
1, 2
(4.998169V)
+FSR 5/2 LSBs (4.996948V)
+FSR 7/2 LSBs (4.995728 V)
111 . . . 110 to 111 . . . 111
111 . . . 110 to 111 . . . 110
111 . . . 100 to 111 . . . 101
AGND + 5/2 LSB (0.003052V)
AGND + 3/2 LSB (0.01832V)
AGND + 1/2 LSB (0.000610V)
000 . . . 010 to 010 . . . 011
000 . . . 001 to 001 . . . 010
000 . . . 000 to 000 . . . 001
+FSR 3/2 LSB
2, 3
(2.499084V)
111 . . . 110 to 111 . . . 111
+2.5
REFERENCE
VREF
V
IN1
V
IN2
*
AGND
TO HIGH
IMPEDANCE
SHA INPUT
TO ADC
REFERENCE
CIRCUITRY
2k
5.5k
5.5k
V
IN2
* IS UNCONNECTED INTERNALLY ON THE AD7889-3
Figure 5. AD7889-3 Analog Input Structure
The designed code transitions occur midway between succes-
sive integer LSB values (i.e., 1/2LSB, 3/2LSBs, 5/2 LSBs).
Output coding is 2s complement binary with 1LSB = FSR/
4096 = 5V/4096 = 1.22mV with VREF = +2.5V. The ideal
input/output transfer function for the AD7889-3 is shown in
Table IV.
Table IV. Ideal Input/Output Code Table for the AD7889-3
Digital Output
Code Transition
Analog Input
+FSR/2 3/2 LSB
1, 2
(2.49817)
+FSR/2 5/2 LSBs (2.49695)
+FSR/2 7/2 LSBs (2.49573)
011 . . . 110 to 011 . . . 111
011 . . . 110 to 011 . . . 110
011 . . . 110 to 011 . . . 101
AGND + 3/2 LSB (0.00183)
AGND + 1/2 LSB (0.00061)
AGND 1/2 LSB (0.00061)
AGND 3/2 LSB (0.00183)
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
FSR/2 + 5/2 LSB (2.49695)
FSR/2 + 3/2 LSB (2.49817)
FSR/2 + 1/2 LSB (2.49939)
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
NOTES
1
FSR is full-scale range and is 5V with VREF = +2.5V.
2
1LSB = FSR/4096 = 1.22mV with VREF = +2.5 V.
MICROPROCESSOR INTERFACING
The AD7889 features a high speed serial interfaces with four
modes of operation, allowing considerable flexibility in inter-
facing to microprocessor systems.
Figures 6, 7 and 8 show some typical interface circuits between
the AD7889 and popular DSP processors. The
CONVST
signal can be generated by a flag pin from
the DSP or by external hardware controlled by a timer.
AD7889 to ADSP-21XX Interface
Figure 6 shows a serial interface between the AD7889 and the
ADSP-21XX family of DSP processors. TheAD7889 is operat-
ing in Mode A (maximum throughput) and the RFS and
SCLK signals are inputs to the DSP. The flag pin FL0 (con-
trolled by an internal timer routine) is used to provide the
CONVST
. Pulsing
CONVST
starts conversion and data is
provided on the subsequent clock edges.
.
AD7889
CONVST
RFS
SDATA
SCLK
ADSP-21XX
RFS0
DR0
SCLK0
FL0
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