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參數資料
| 型號： | AD7890SQ-2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 20 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 8-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, CERDIP-24 |
| 文件頁數： | 11/20頁 |
| 文件大小： | 302K |
| 代理商： | AD7890SQ-2 |
AD7890
–11–
REV. A
SCLK (O)
CONVST (I)
THREE-STATE
RFS (O)
DATA OUT (O)
TRACK/HOLD
GOES INTO HOLD
t
CONVERT
NOTE
(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.
Figure 4. Self-Clocking {Master) Mode Conversion Sequence
When using the device in the External-Clocking Mode, the out-
put register can be read at any time and the most up-to-date
conversion result will be obtained. However, reading data from
the output register or writing data to the Control Register dur-
ing conversion or during the 500 ns prior to the next
CONVST
will result in reduced performance from the part. A read opera-
tion to the output register has most effect on performance with
the signal-to-noise ratio likely to degrade especially when higher
serial clock rates are used while the code flicker from the part
will also increase (see AD7890 Performance section).
Figure 5 shows the timing and control sequence required to
obtain optimum performance from the part in the external
clocking mode. In the sequence shown, conversion is initiated
on the rising edge of
CONVST
and new data is available in the
output register of the AD7890 5.9
μ
s later. Once the read oper-
ation has taken place, a further 500 ns should be allowed before
the next rising edge of
CONVST
to optimize the settling of the
track/hold before the next conversion is initiated. T he diagram
shows the read operation and the write operation taking place in
parallel. On the sixth falling edge of SCLK in the write sequence
the internal pulse will be initiated. Assuming MUX OUT is
connected to SHA IN, 2
μ
s are required between this sixth fall-
ing edge of SCLK and the rising edge of
CONVST
to allow for
the full acquisition time of the track/hold amplifier. With the
serial clock rate at its maximum of 10 MHz, the achievable
throughput rate for the part is 5.9
μ
s (conversion time) plus
0.6
μ
s (six serial clock pulses before internal pulse is initiated)
plus 2
μ
s (acquisition time). T his results in a minimum through-
put time of 8.5
μ
s (equivalent to a throughput rate of 117 kHz).
If the part is operated with a slower serial clock, it will impact
the achievable throughput rate for optimum performance.
SCLK
CONVST
CONVERSION IS
INITIATED AND
TRACK/HOLD GOES
INTO HOLD
CONVERSION
ENDS 5.9
μ
s
LATER
SERIAL READ
& WRITE
OPERATIONS
READ & WRITE
OPERATIONS SHOULD END
500ns PRIOR TO NEXT
RISING EDGE OF CONVST
RFS
TFS
NEXT
CONVERSION
START COMMAND
t
CONVERT
500ns MIN
Figure 5. External Clocking (Slave) Mode Timing
Sequence for Optimum Performance
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