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參數資料
| 型號： | AD790SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Fast, Precision Comparator |
| 中文描述： | COMPARATOR, 1500 uV OFFSET-MAX, 60 ns RESPONSE TIME, CDIP8 |
| 封裝： | HERMETIC SEALED, CERDIP-8 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 211K |
| 代理商： | AD790SQ |
SINGLE SUPPLY
AD790J/A
T yp
AD790K/B
T yp
AD790S
T yp
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Units
RESPONSE CHARACT ERIST IC
Propagation Delay, t
PD
100 mV Step
5 mV Overdrive
T
MIN
to T
MAX
45
50
50/60
45
50
50/60
45
50
65
ns
ns
OUT PUT CHARACT ERIST ICS
Output HIGH Voltage, V
OH
1.6 mA Source
6.4 mA Source
T
MIN
to T
MAX
1.6 mA Sink
6.4 mA Sink
T
MIN
to T
MAX
4.65
4.45
4.65
4.45
4.65
4.45
4.3
4.3
4.3
4.3
4.3
4.3
V
V
V
V
V
Output LOW Voltage, V
OL
0.35
0.44
0.35
0.44
0.35
0.44
0.5
0.5
0.5
0.5
0.5
0.5
INPUT CHARACT ERIST ICS
Offset Voltage
2
0.45
1.5
2.0
0.75
5
7
0.25
0.3
0.35
0.6
0.85
0.65
3.5
5
0.15
0.2
0.45
1.5
2.0
1.0
5
8
0.25
0.4
mV
mV
mV
μ
A
μ
A
μ
A
μ
A
T
MIN
to T
MAX
T
to T
Either Input
T
MIN
to T
MAX
Hysteresis
3
Bias Current
0.3
0.5
2.7
0.3
0.5
2.0
0.3
0.7
2.7
Offset Current
0.04
0.02
0.04
T
MIN
to T
MAX
Power Supply
Rejection Ratio DC
4.5 V
≤
V
S
≤
5.5 V
T
MIN
to T
MAX
80
76/
76
88
90
86
82
100
93
80
76
90
85
dB
dB
Input Voltage Range
Differential Voltage
Common Mode
Input Impedance
6
V
S
+V
S
–2 V
6
V
S
+V
S
–2 V
6
V
S
+V
S
–2 V V
V
0
0
0
20
i
2
20
i
2
20
i
2
M
i
pF
LAT CH CHARACT ERIST ICS
Latch Hold T ime, t
H
Latch Setup T ime, t
S
LOW Input Level, V
IL
HIGH Input Level, V
IH
Latch Input Current
25
5
35
10
0.8
25
5
35
10
0.8
25
5
35
10
0.8
ns
ns
V
V
μ
A
μ
A
T
MIN
to T
MAX
T
MIN
to T
MAX
1.6
1.6
1.6
2.3
5
7
2.3
3.5
5
2.3
5
8
T
MIN
to T
MAX
SUPPLY CHARACT ERIST ICS
Supply Voltage
4
Quiescent Current
Power Dissipation
T
MIN
to T
MAX
4.5
7
12
60
4.5
7
12
60
4.7
7
12
60
V
mA
mW
10
10
10
T EMPERAT URE RANGE
Rated Performance
T
MIN
to T
MAX
0 to +70/–40 to +85
0 to +70/–40 to +85
–55 to +125
°
C
NOT ES
1
Pin 1 tied to Pin 8, and Pin 4 tied to Pin 6.
2
Defined as the average of the input voltages at the low to high and high to low transition points. Refer to Figure 14.
3
Defined as half the magnitude between the input voltages at the low to high and high to low transition points. Refer to Figure 14.
4
–V
S
must not be connected above ground.
All min and max specifications are guaranteed. Specifications shown in
boldface
are tested on all production units at final test.
Specifications subject to change without notice.
AD790
REV. B
–3–
(Operation @ +25
8
C and +V
S
= V
LOGIC
= +5 V, –V
S
= 0 V unless otherwse noted)
1
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相關代理商/技術參數 |
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