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參數資料
| 型號： | AD7922AUJ-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | ER 2C 2#16S PIN RECP |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-193BA, TSOT-8 |
| 文件頁數： | 7/32頁 |
| 文件大小： | 386K |
| 代理商： | AD7922AUJ-R2 |
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AD7912/AD7922
TIMING SPECIFICATIONS
Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
V
DD
= 2.35 V to 5.25 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
Limit at T
MIN
,
T
MAX
f
SCLK1
10
kHz min
2
18
MHz max
t
CONVERT
16 × t
SCLK
AD7922
14 × t
SCLK
AD7912
t
QUIET
30
ns min
Minimum quiet time required between bus relinquish and start of next conversion
t
1
15
ns min
Minimum CS pulse width
t
2
10
ns min
CS to SCLK setup time
t
33
30
ns max
Delay from CS until DOUT three-state is disabled
t
43
45
ns max
DOUT access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min
SCLK low pulse width
t
6
0.4 t
SCLK
ns min
SCLK high pulse width
t
74
10
ns min
SCLK to DOUT valid hold time
t
8
5
ns min
DIN setup time prior to SCLK falling edge
t
9
6
ns min
DIN hold time after SCLK falling edge
t
105
30
ns max
SCLK falling edge to DOUT three-state
10
ns min
SCLK falling edge to DOUT three-state
t
POWER-UP6
1
μs max
Power-up time from full power-down
Rev. 0 | Page 7 of 32
Unit
Description
1
Mark/space ratio for SCLK input is 40/60 to 60/40.
2
Minimum f
SCLK
at which specifications are guaranteed.
3
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross V
IH
or V
IL
voltage.
4
Measured with a 50 pF load capacitor.
5
T
10
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
See the Power-Up Time section.
TIMING DIAGRAMS
0
200
μ
A
I
OL
200
μ
A
I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
0
SCLK
V
IH
V
IL
DOUT
t
4
Figure 3. Access Time after SCLK Falling Edge
0
SCLK
V
IH
V
IL
DOUT
t
7
Figure 4. Hold Time after SCLK Falling Edge
0
SCLK
1.6V
DOUT
t
10
Figure 5. SCLK Falling Edge to DOUT Three-State
相關PDF資料 |
PDF描述 |
|---|---|
| AD7912AUJ-R2 | 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs |
| AD7922AUJ-REEL7 | Circular Connector; No. of Contacts:7; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:16S; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle |
| AD7912AUJ-REEL7 | Circular Connector; No. of Contacts:5; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:16S; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:16S-8 RoHS Compliant: No |
| AD7912 | 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs |
| AD7912ARM | 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 10-/12-Bit ADCs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7922AUJ-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 8-Pin TSOT T/R |
| AD7922AUJ-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 8-Pin TSOT T/R 制造商:Rochester Electronics LLC 功能描述:DUAL 12-BIT, 1MSPS, ADC I.C - Tape and Reel |
| AD7922AUJZ-REEL7 | 功能描述:IC ADC DUAL 12BIT 2CH TSOT-23-8 RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7923 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP |
| AD7923_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 200 kSPS 12-Bit ADC with Sequencer in 16-Lead TSSOP |
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