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參數資料
| 型號： | AD7924 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4通道，1 MSPS的，8-/10-/12-Bit ADC的16與序列鉛TSSOP封裝 |
| 文件頁數： | 17/24頁 |
| 文件大小： | 411K |
| 代理商： | AD7924 |
AD7904/AD7914/AD7924
–17–
REV. 0
16-bit word. This 16-bit data stream consists of two leading
zeros, two address bits indicating which channel the conversion
result corresponds to, followed by the 12 bits of conversion data
for the AD7924 (10 bits of data for the AD7914 and 8 bits of data
for the AD7904, each followed by 2 and 4 trailing zeros, respec-
tively). For applications where power consumption is of concern,
the power-down modes should be used between conversions or
bursts of several conversions to improve power performance.
See the Modes of Operation section of the data sheet.
SERIAL
INTERFACE
AD780
2.5V
AD7904/
AD7914/
AD7924
0.1 F
C/ P
0.1 F
10 F
3V
SUPPLY
5V
SUPPLY
0.1 F
10 F
AGND
V
DD
V
IN
0
V
IN
3
0V TO REF
IN
SCLK
DOUT
CS
DIN
V
DRIVE
REF
IN
NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND
Figure 10. Typical Connection Diagram
Analog Input Selection
Any one of four analog input channels may be selected for con-
version by programming the multiplexer with the address bits
ADD1 and ADD0 in the Control Register. The channel con-
figurations are shown in Table II.
The AD7904/AD7914/AD7924 may also be configured to auto-
matically cycle through a number of channels as selected. The
sequencer feature is accessed via the SEQ1 and SEQ0 bits in the
Control Register, see Table IV. The AD7904/AD7914/AD7924
can be programmed to continuously convert on a number of
consecutive channels in ascending order from Channel 0 to a
selected final channel as determined by the channel address bits
ADD1 and ADD0. This is possible if the SEQ1 and SEQ0 bits
are set to 1,1. The next serial transfer will then act on the sequence
programmed by executing a conversion on Channel 0. The next
serial transfer will result in a conversion on Channel 1, and so
on, until the channel selected via the address bits ADD1, ADD0
is reached.
It is not necessary to write to the Control Register again once a
sequencer operation has been initiated. The WRITE bit must be
set to zero or the DIN line tied low to ensure the Control Regis-
ter is not accidently overwritten, or the sequence operation
interrupted. If the Control Register is written to at any time
during the sequence then it must be ensured that the SEQ1 and
SEQ0 bits are set to 1,0 to avoid interrupting the automatic
conversion sequence. This pattern will continue until such time
as the AD7904/AD7914/AD7924 is written to and the SEQ1
and SEQ0 bits are configured with any bit combination except
1,0 resulting in the termination of the sequence. If uninter-
rupted, however (WRITE bit = 0, or WRITE bit = 1 and SEQ1
and SEQ0 bits are set to 1,0), then upon completion of the
sequence, the AD7904/AD7914/AD7924 sequencer will return
to the Channel 0 and commence the sequence again.
Regardless of which channel selection method is used, the 16-bit
word output from the AD7924 during each conversion will always
contain two leading zeros, two channel address bits that the con-
version result corresponds to, followed by the 12-bit conversion
result; the AD7914 will output two leading zeros, two channel
address bits that the conversion result corresponds to, followed by
the 10-bit conversion result and two trailing zeros; the AD7904 will
output two leading zeros, two channel address bits that the conver-
sion result corresponds to, followed by the 8-bit conversion result
and four trailing zeros. See the Serial Interface section.
Digital Inputs
The digital inputs applied to the AD7904/AD7914/AD7924 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the V
DD
+ 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and
CS
not being restricted
by the V
DD
+ 0.3 V limit is the fact that power supply sequenc-
ing issues are avoided. If
CS
, DIN, or SCLK are applied before
V
DD
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to V
DD
.
V
DRIVE
The AD7904/AD7914/AD7924 also have the V
DRIVE
feature.
V
DRIVE
controls the voltage at which the serial interface oper-
ates. V
DRIVE
allows the ADC to easily interface to both 3 V and
5 V processors. For example, if the AD7904/AD7914/AD7924
were operated with a V
DD
of 5 V, the V
DRIVE
pin could be pow-
ered from a 3 V supply. The AD7904/AD7914/AD7924 have
R3
R2
R4
REF
IN
V
IN
0
V
IN
3
AD7904/
AD7914/
AD7924
DSP/ P
V
DD
0.1 F
V
V
DD
V
DRIVE
DOUT
TWOS
COMPLEMENT
+REF
IN
REF
IN
–REF
IN
011…111
000…000
100…000
(= 0V)
(= 2 REF
IN
)
0V
V
R1
R1 R2 R3 R4
V
DD
V
REF
Figure 9. Handling Bipolar Signals
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