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參數資料
| 型號： | AD7924 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 16-Lead TSSOP |
| 中文描述： | 4通道，1 MSPS的，8-/10-/12-Bit ADC的16與序列鉛TSSOP封裝 |
| 文件頁數： | 6/24頁 |
| 文件大小： | 411K |
| 代理商： | AD7924 |
–6–
REV. 0
(AV
= V
= 2.7 V to 5.25 V, REF
IN
= 2.5 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
AD7924
–
SPECIFICATIONS
Parameter
B Version
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)
2
f
IN
= 50 kHz Sine Wave, f
SCLK
= 20 MHz
@ 5 V
@ 3 V Typically 69.5 dB
70
69
70
–77
–73
–78
–76
dB min
dB min
dB min
dB max
dB max
dB max
dB max
Signal to Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
2
@ 5 V Typically –84 dB
@ 3 V Typically –77 dB
@ 5 V Typically –86 dB
@ 3 V Typically –80 dB
fa = 40.1 kHz, fb = 41.5 kHz
Peak Harmonic or Spurious Noise
(SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
2
Full Power Bandwidth
–90
–90
10
50
–85
8.2
1.6
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
f
IN
= 400 kHz
@ 3 dB
@ 0.1 dB
DC ACCURACY
2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REF
IN
Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2
×
REF
IN
Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
12
±
1
–0.9/+1.5
Bits
LSB max
LSB max
Guaranteed No Missed Codes to 12 Bits
Straight Binary Output Coding
Typically
±
0.5 LSB
±
8
±
0.5
±
1.5
±
0.5
LSB max
LSB max
LSB max
LSB max
–REF
IN
to +REF
IN
Biased about REF
IN
with
Twos Complement Output Coding
±
1.5
±
0.5
±
8
±
0.5
±
1
±
0.5
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Typically
±
0.8 LSB
ANALOG INPUT
Input Voltage Range
0 to REF
IN
0 to 2
×
REF
IN
V
±
1
20
V
RANGE Bit Set to 1
RANGE Bit Set to 0, V
DD
/V
DRIVE
= 4.75 V to 5.25 V
DC Leakage Current
Input Capacitance
μ
A max
pF typ
REFERENCE INPUT
REF
IN
Input Voltage
DC Leakage Current
REF
IN
Input Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
2.5
±
1
36
V
μ
A max
k
typ
±
1% Specified Performance
f
SAMPLE
= 1 MSPS
0.7
×
V
DRIVE
0.3
×
V
DRIVE
±
1
10
V min
V max
μ
A max
pF max
Typically 10 nA, V
IN
= 0 V or V
DRIVE
V
DRIVE
– 0.2
0.4
±
1
10
Straight (Natural) Binary
Twos Complement
V min
V max
μ
A max
pF max
I
SOURCE
= 200
μ
A, V
DD
= 2.7 V to 5.25 V
I
SINK
= 200
μ
A
Coding Bit Set to 1
Coding Bit Set to 0
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