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參數資料
| 型號： | AD7993BRU-1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP |
| 中文描述： | 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153-AB, TSSOP-16 |
| 文件頁數： | 19/27頁 |
| 文件大小： | 277K |
| 代理商： | AD7993BRU-1 |
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AD7994/AD7993
–19–
REV. PrF
PRELIMINARY TECHNICAL DATA
Table XIb. Alert Status Register Bit Function
Description
Bit Mnemonic Comment
D0 CH1
LO
Violation of DATA
LOW
limit on Channel
1 if this bit set to 1, no violation if 0.
D1 CH1
HI
Violation of DATA
HIGH
limit on Chan
nel 1 if this bit set to 1, no violation if 0.
D2 CH2
LO
Violation of DATA
LOW
limit on Channel
2 if this bit set to 1, no violation if 0.
D3 CH2
HI
Violation of DATA
HIGH
limit on Chan
nel 2 if this bit set to 1, no violation if 0.
D4 CH3
LO
Violation of DATA
LOW
limit on Channel
3 if this bit set to 1, no violation if 0.
D5 CH3
HI
Violation of DATA
HIGH
limit on Chan
nel 3 if this bit set to 1, no violation if 0.
Violation of DATA
LOW
limit on Channel
4 if this bit set to 1, no violation if 0.
max conversion results, the Alert_Flag bit, D15, can be
used to indicate that an alert has happened on another one
of the Input channels.
It must be noted that on power-up, the contents of the
DATA
HIGH
register for each channel will be fullscale,
while the contents of the DATA
LOW
registers will be
zeroscale, by default minimum and maximum conversion
values being stored in this way will be lost if power is
removed or cycled.
When using the limit registers to store the min and max
conversion results, the Alert_Flag bit, D15, is used to
indicate that an alert has happened on another one of the
Input channels. If the Alert_Flag bit is set to 1, it will be
reset when the Conversion result returns to a value at least
N LSBs above the DATA
LOW
Register value or below the
DATA
LOW
Register value or if bits D2 and D1 of the
Configuration Register are set to 1. The Alert_Flag bit in
the limit registers is useful if the user is not reading from
the conversion result register when reading the min and
max conversion results from the limit registers.
ALERT STATUS REGISTER
The Alert Status Register is a 8-bit read/write register,
which provides information on an Alert event. If a conver-
sion results in activating the ALERT pin or the Alert_Flag
bit in the Conversion Result Register, as described in the
Limit Registers section, then the Alert Status Register may
be read to gain further information. It contains 2 status
bits per channel, one corresponding to the DATA
HIGH
limit and the other to the DATA
LOW
limit. Whichever bit
has a status of 1 will show where the violation occured, i.e.
on which channel and whether on upper or lower limit. If
a second alert event occurs on the other channel between
receiving the first alert and interrogating the Alert Status
register then the corresponding bit for that Alert event will
be set also.
The entire contents of the Alert Status register may be
cleared by writing 1,1, to bits D2 and D1 in the Configu-
ration register as shown in Table VI. This may also be
acheived by ‘writing’ all 1’s to the Alert Status Register
itself. This means that if the Alert Status Register is ad-
dressed for a write operation which is all 1’s, then the
contents of the Alert Status Register will then be cleared
or resest to all 0’s. Alternatively, an individual active Alert
bit(s) may be reset within the Alert Status Register by
performing a write of ‘1’ to that bit alone. The advantage
of this is that once an Alert event has been serviced, that
particular bit can be reset, e.g. CH1
LO
, without clearing
the entire contents of the Alert Status Register, thus pre-
serving the status of any additional Alert, e.g. CH2
HI
,
which may have occured while servicing the first. If it is
not necessary to clear an Alert directly after servicing then
obviously the Alert Status register may be read again im-
mediately to look for any new Alerts, bearing in mind that
the one just serviced will still be active.
Table XIa. Alert Status Register
D7
D6
D5
D4
D3
D2
D1
D0
CH4
HI
CH4
LO
CH3
HI
CH3
LO
CH2
HI
CH2
LO
CH1
HI
CH1
LO
D6 CH4
LO
D7 CH4
HI
Violation of DATA
HIGH
limit on Chan
nel 4 if this bit set to 1, no violation if 0.
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