
REV. B
AD8033/AD8034
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8033/AD8034 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AMBIENT TEMPERATURE – C
–60
–40
–20
0
20
40
60
80
100
2.0
1.5
M
1.0
0.5
0.0
SOIC-8
SOT-23-8
SC70-5
Figure 2. Maximum Power Dissipation vs.
Temperature for a Four-Layer Board
ORDERING GUIDE
WARNING!
ESD SENSITIVE DEVICE
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8033/AD8034
packages is limited by the associated rise in junction temperature
(
T
J
) on the die. The plastic that encapsulates the die will locally
reach the junction temperature. At approximately 150
°
C, which is
the glass transition temperature, the plastic will change its proper-
ties. Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8033/AD8034. Exceeding a
junction temperature of 175
°
C for an extended period of time can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (
JA
),
ambient temperature (
T
A
), and the total power dissipated in the
package (
P
D
) determine the junction temperature of the die.
The junction temperature can be calculated as follows
=
+
(
The power dissipated in the package (
P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (
V
S
) times the quiescent current (
I
S
).
Assuming the load (
R
L
) is referenced to midsupply, then the total
drive power is
V
S
/2
I
OUT
,
some of which is dissipated in the
package and some in the load (
V
OUT
I
OUT
). The difference
between the total drive power and the load power is the drive
power dissipated in the package:
P
P
RMS output voltages should be considered. If
R
L
is referenced
to
V
S–
, as in single-supply operation, then the total drive power
is
V
S
I
OUT
.
If the rms signal levels are indeterminate, consider the worst
case, when
V
OUT
=
V
S
/4 for
R
L
to midsupply:
P
In single-supply operation with
R
L
referenced to
V
S–
,
worst case
is
V
OUT
=
V
S
/2.
T
T
A
D
A
J
J
×
)
P
θ
Quiescent Power
V
I
S
=
×
[
Total Drive Power
+
(
V
S
OUT
)
×
(
/
2
Load Power
V
OUT
D
=
–
)
V
R
R
D
S
L
L
]
+
(
)
[
]
[
]
/
–
/
2
V
(
I
V
R
D
S
S
S
L
=
×
)
+
(
)
/
/
4
2
Airflow will increase heat dissipation, effectively reducing
JA
.
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes will reduce
the
JA
. Care must be taken to minimize parasitic capacitances at
the input leads of high speed op amps as discussed in the Layout,
Grounding, and Bypassing Considerations section.
Figure 2 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8 (125
°
C/W),
SC70
(210
°
C/W),
and
SOT-23-8 (160
°
C/W) packages on a JEDEC
standard 4-layer board.
JA
values are approximations.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8033/AD8034 will likely cause catastrophic failure.
Model
AD8033AR
AD8033AR-REEL
AD8033AR-REEL7
AD8033AKS-REEL
AD8033AKS-REEL7
AD8034AR
AD8034AR-REEL7
AD8034AR-REEL
AD8034ART-REEL
AD8034ART -REEL7
Temperature Range
+85oC
+85oC
+85oC
+85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
+85oC
+85oC
–40oC to
Package
Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SC70
5-Lead SC70
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOT-23
8-Lead SOT-23
Package Outline
R-8
R-8
R-8
KS-5
KS-5
R-8
R-8
R-8
RT-8
RT-8
Branding
Information
H3B
H3B
HZA
HZA
–40oC to
–40oC to
–40oC to
–40oC to
–40oC to