- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373931 > AD803 (Analog Devices, Inc.) Clock Recovery and Data Retiming Phase-Locked Loop(時鐘恢復(fù)和重定時PLL) PDF資料下載
參數(shù)資料
| 型號： | AD803 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Clock Recovery and Data Retiming Phase-Locked Loop(時鐘恢復(fù)和重定時PLL) |
| 中文描述： | 時鐘恢復(fù)和數(shù)據(jù)重定時鎖相環(huán)（時鐘恢復(fù)和重定時鎖相環(huán)） |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 129K |
| 代理商： | AD803 |
–2–
REV. 0
AD803–SPECIFICATIONS
(V
CC
= V
MIN
to V
MAX
, V
EE
= GND, T
A
= T
MIN
to T
MAX
, Loop Damping Factor = 5, unless
otherwise noted)
Parameter
Condition
Min
Typ
Max
Units
NOMINAL DATA RATE
CAPTURE RANGE/TRACKING RANGE
1
20.48
Mbps
19.10
20.50
Mbps
STATIC PHASE ERROR
2
23
–1 PRN Sequence
ρ
= 1
2
23
–1 PRN Sequence
15
Degrees
OUTPUT JITTER
2.5
3.0
Degrees rms
Degrees rms
5.8
JITTER TOLERANCE
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
795
79.5
7.95
0.95
955
95.5
9.55
1.1
UI p-p
UI p-p
UI p-p
UI p-p
JITTER TRANSFER
Damping Factor Capacitor, C
D
Peaking
Bandwidth
Damping Factor Capacitor, C
D
Peaking
Bandwidth
Damping Factor Capacitor, C
D
Peaking
Bandwidth
ζ
= 1, Nominal
15
1.6
34
0.47
0.06
28
1.5
0.02
28
nF
dB
kHz
μ
F
dB
kHz
μ
F
dB
kHz
ζ
= 5, Nominal
ζ
= 10, Nominal
RECOVERED CLOCK SKEW
CLKOUT to DATAOUT Rising Edge
CLKOUT to DATAOUT Falling Edge
5.5
13.6
ns
ns
1.95
TRANSITIONLESS DATA RUN
Phase Drift
500-Bit Period Block
1000-Bit Period Block
ρ
= 1/2
5.0
10.0
Degrees
Degrees
ACQUISITION TIME
300,000
Bit Periods
POWER SUPPLY
Voltage (V
MIN
to V
MAX
)
Current
4.5
5.0
40
5.5
50
60
Volts
mA
mA
T
A
= +25
°
C, V
CC
= +5.0 V
INPUT VOLTAGE LEVELS
Input Logic High, V
IH
Input Logic Low, V
IL
OUTPUT VOLTAGE LEVELS
Output Logic High, V
OH
Output Logic Low, V
OL
INPUT CURRENT LEVELS
Input Logic High, I
IH
Input Logic Low, I
IL
OUTPUT SLEW TIMES, CLKOUT
Rise Time, t
R
Fall Time, t
F
OUTPUT SLEW TIMES, DATAOUT
Rise Time, t
R
Fall Time, t
F
SYMMETRY
Recovered Clock Output
V
CC
= +5 V
±
5%
2.0
Volts
Volts
0.8
V
CC
= +5 V
±
5%
I
OH
= –0.4 mA
I
OL
= 4 mA
2.4
Volts
Volts
0.43
–0.06
–0.65
mA
mA
10%–90%
90%–10%
11
5
15.7
6.9
ns
ns
10%–90%
90%–10%
13
5.7
18.2
8.6
ns
ns
±
5%
Deviation
from 50%
NOTES
1
No input jitter is applied to the input data for this specification.
Specifications subject to change without notice.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8041AR-REEL | 160 MHz Rail-to-Rail Amplifier with Disable |
| AD8041 | 160 MHz Rail-to-Rail Amplifier with Disable |
| AD8041-EB | 160 MHz Rail-to-Rail Amplifier with Disable |
| AD8041AN | 160 MHz Rail-to-Rail Amplifier with Disable |
| AD8041AR | 160 MHz Rail-to-Rail Amplifier with Disable |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8030 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, High Speed Rail-to-Rail Input/Output Amplifier |
| AD80305BBCZ | 制造商:Analog Devices 功能描述:- Rail/Tube |
| AD80305XBCZ | 制造商:Analog Devices 功能描述:X-GRADE VERSION OF AD80305BBCZ, CATALINA RFIC, 1X1, 144CSBGA - Rail/Tube |
| AD8030AR | 功能描述:IC AMP GP R-R DUAL LP 8SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:100 系列:- 放大器類型:通用 電路數(shù):1 輸出類型:- 轉(zhuǎn)換速率:0.2 V/µs 增益帶寬積:- -3db帶寬:- 電流 - 輸入偏壓:100pA 電壓 - 輸入偏移:30µV 電流 - 電源:380µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):±2 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SO 包裝:管件 |
| AD8030AR | 制造商:Analog Devices 功能描述:AMP LOW POWER RRI/O 8030 SOIC8 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。