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參數(shù)資料
| 型號(hào)： | AD8062AR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter 20-SSOP/QSOP |
| 中文描述： | DUAL OP-AMP, 6000 uV OFFSET-MAX, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 314K |
| 代理商： | AD8062AR-REEL |
AD8061/AD8062/AD8063
–12–
REV. C
50mV/DIV
V
= 5V
G = 1
R
L
= 1k
0
5
10
40
45
50
2.6V
TIME
–
ns
2.5V
2.4V
35
30
25
20
15
TPC 37. 200 mV Step Response
1V/DIV
V
S
= 5V
G = 2
R
L
= R
= 1k
V
IN
= 2V p-p
0
5
10
40
45
50
TIME
–
ns
35
30
25
20
15
4.5V
2.5V
0.5V
TPC 38. 2 V Step Response
CIRCUIT DESCRIPTION
The AD8061/AD8062/AD8063 family are very high-speed volt-
age feedback op amps. The high slew rate input stage is a true
single-supply topology, capable of sensing signals at or below
the minus supply rail. The rail-to-rail output stage can pull
within 30 mV of either supply rail when driving light loads and
within 0.3 V when driving 150
. High-speed performance is
maintained at supply voltages as low as 2.7 V.
Headroom Considerations
These amplifiers are designed for use in low-voltage systems. To
obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier’s headroom limits.
The AD806x’s input common-mode voltage range extends from
the negative supply voltage (actually 200 mV below this), or
“ground” for single supply operation, to within 1.8 V of the
positive supply voltage. Thus, at a gain of 2, the AD806x can
provide full “rail-to-rail” output swing for supply voltage as low
as 3.6 V, assuming the input signal swing from –V
S
(or ground)
to +V
S
/2. At a gain of 3, the AD806x can provide a rail-to-rail
output range down to 2.7 V total supply voltage.
Exceeding the headroom limit is not a concern for any inverting
gain on any supply voltage, as long as the reference voltage at
the amplifier’s positive input lies within the amplifier’s input
common-mode range.
The input stage will be the headroom limit for signals when the
amplifier is used in a gain of 1 for signals approaching the
positive rail. Figure 3 shows a typical offset voltage versus
input common-mode voltage for the AD806x amplifier on a
5 V supply. Accurate dc performance is maintained from about
200 mV below the minus supply to within 1.8 V of the positive
supply. For high-speed signals, however, there are other consid-
erations. Figure 4 shows –3 dB bandwidth versus dc input
V
CM
–
V
V
O
–
–
4.0
–
3.6
–
3.2
–
2.8
–
2.4
–
2.0
–
1.6
–
1.2
–
0.8
–
0.4
–
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 3. V
OS
vs. Common-Mode Voltage, V
S
= 5 V
V
CM
= 3.0
V
CM
= 3.1
V
CM
= 3.2
V
CM
= 3.3
V
CM
= 3.4
FREQUENCY
–
MHz
2
–
8
0.1
G
–
–
4
0
–
2
–
6
1
10
100
1000
10000
Figure 4. Unity Gain Follower Bandwidth vs. Input
Common Mode, V
S
= 5 V
voltage for a unity gain follower. As the common-mode voltage
approaches the positive supply, the amplifier holds together
well, but the bandwidth begins to drop at 1.9 V within +V
S
.
This can manifest itself in increased distortion or settling time.
TPC 10 plots the distortion of a 1V p-p signal with the AD806x
amplifier used as a follower on a 5V supply versus signal common-
mode voltage. Distortion performance is maintained until the
input signal center voltage gets beyond 2.5 V, as the peak of the
input sine wave begins to run into the upper common-mode
voltage limit. Higher frequency signals require more headroom
than the lower frequencies to maintain distortion performance.
Figure 5 illustrates how the rising edge settling time for the
amplifier configured as a unity gain follower stretches out as the
top of a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.
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| AD8062AR-REEL7 | 制造商:Analog Devices 功能描述:OP Amp Dual Volt Fdbk R-R O/P 8V 8-Pin SOIC N T/R 制造商:Rochester Electronics LLC 功能描述:SOIC DUAL, RAIL-TO-RAIL VLTG-FDBK AMP - Tape and Reel |
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