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參數(shù)資料
| 型號(hào)： | AD8138ARZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Distortion Differential ADC Driver |
| 中文描述： | LINE DRIVER, PDSO8 |
| 封裝： | LEAD FREE, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 318K |
| 代理商： | AD8138ARZ-RL |
AD8138
When using the AD8138 in gain configurations where
R
Rev. F | Page 18 of 24
G
F
R
of one feedback network is unequal to
R
G
F
R
of the other network, there is a differential output noise due to
input-referred voltage in the V
OCM
circuitry. The output noise is
defined in terms of the following feedback terms (refer to
Figure 42):
R
+
G
F
G
R
R
=
β
1
for OUT to +IN loop, and
R
+
G
F
G
R
R
=
β
2
for +OUT to IN loop. With these defined,
β
+
β
β
β
=
2
1
2
1
,
,
2
OCM
V
nIN
dm
nOUT
V
V
where
V
nOUT, dm
is the output differential noise, and
the input-referred voltage noise in V
OCM
.
is
COM
V
,
nIN
V
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback
networks (R
F
/R
G
) are mismatched, the internal common-mode
feedback loop still forces the outputs to remain balanced. The
amplitudes of the signals at each output remains equal and 180°
out of phase. The input-to-output differential-mode gain varies
proportionately to the feedback mismatch, but the output
balance is unaffected.
Ratio matching errors in the external resistors result in a
degradation of the circuit’s ability to reject input common-
mode signals, much the same as for a four-resistor difference
amplifier made from a conventional op amp.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. For the G = 1 case, with
a ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of about 40 dB, worst-case differential mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
The effective input impedance of a circuit such as the one in
Figure 42, at +DIN and –DIN, depends on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (
R
IN, dm
)
between the inputs (+D
IN
and D
IN
) is simply
R
IN, dm
=2 ×
R
G
In the case of a single-ended input signal (for example if D
IN
is
grounded and the input signal is applied to +D
IN
), the input
impedance becomes
(
)
+
×
=
F
G
F
G
R
dm
IN
R
R
R
R
2
1
,
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor R
G
.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The AD8138 is optimized for level-shifting, ground-referenced
input signals. For a single-ended input, this would imply, for
example, that the voltage at D
IN
in Figure 42 would be 0 V
when the amplifier’s negative power supply voltage (at V) is
also set to 0 V.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The AD8138’s V
OCM
pin is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V). Relying on this internal bias results
in an output common-mode voltage that is within about
100 mV of the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
The output common-mode offset listed in the Specifications
section assumes the V
OCM
input is driven by a low impedance
voltage source.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the pin and bondwire
inductance of the AD8138, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to
place a small capacitor across each of the feedback resistors. The
added capacitance should be small to avoid destabilizing the
amplifier. An alternative technique is to place a small resistor in
series with the amplifier’s outputs, as shown in Figure 40.
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