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參數資料
型號: AD8151-EVAL
廠商: Analog Devices, Inc.
英文描述: GPA/SK 300X280X1,5...
中文描述: 33 × 17,3.2 Gb / s的數字交叉點開關
文件頁數: 18/36頁
文件大小: 5326K
代理商: AD8151-EVAL
AD8151
–18–
REV. 0
V
CC
V
EE
DISABLE
I
OUT
OUTyyP
OUTyyN
V
CC
2V
V
EE
Figure 11. Simplified Output Circuit
To ensure proper operation, all outputs (including unused output)
must be pulled high using external pull-up networks to a level
within the output compliance range. If outputs from multiple
AD8151s are wired together, a single pull-up network may be
used for each output bus. The pull-up network should be chosen
to keep the output voltage levels within the output compliance
range at all times. Recommended pull-up networks to produce
PECL/ECL 100 k
and 10 k
compatible outputs are shown
in Figure 12. Alternatively, a separate supply can be used to
provide V
COM
; making R
COM
and D
COM
unnecessary.
V
CC
R
COM
V
COM
R
L
OUTyyN
OUTyyP
AD8151
R
L
D
COM
V
CC
V
COM
R
L
OUTyyN
OUTyyP
AD8151
R
L
Figure 12. Output Pull-Up Networks: a) ECL 100 k
,
b) ECL 10 k
The output levels are simply:
V
OH
=
V
COM
V
OL
=
V
COM
– I
OUT
R
L
V
SWING
= V
OH
– V
OL
= I
OUT
R
L
V
COM
=
V
CC
– I
OUT
R
COM
(
100 k
Mode
)
V
COM
=
V
CC
– V
(
D
COM
)
(
10 k
Mode
)
The common-mode adjustment element (R
COM
or D
COM
) may
be omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(V
COM
) to ground.
When busing together the outputs of multiple AD8151s or when
running at high data rates, double termination of its outputs is
recommended to mitigate the impact of reflections due to open
transmission line stubs and the lumped capacitance of the
AD8151 output pins. A possible connection is shown in Figure
13; the bypass capacitors provide an ac short from the common
nodes of the termination resistors to ground. To maintain signal
fidelity at high data rates, the stubs connecting the output pins
to the output transmission lines or load resistors should be as
short as possible.
V
CC
R
COM
V
COM
R
L
OUTyyN
OUTyyP
AD8151
R
L
Z
O
Z
O
OUTyyN
OUTyyP
AD8151
Z
O
Z
O
R
L
R
L
RECEIVER
Figure 13. Double Termination of AD8151 Outputs
In this case, the output levels are:
V
OH
=
V
COM
(1/4)
I
OUT
R
L
V
OL
=
V
COM
(3/4)
I
OUT
R
L
V
SWING
=
V
OH
V
OL
= (1/2)
I
OUT
R
L
Output Current Set Pin (REF)
A simplified schematic of the reference circuit is shown in Fig-
ure 14. A single external resistor connected between the REF
pin and V
EE
determines the output current for all output stages.
This feature allows a choice of pull-up networks and transmission
line characteristic impedances while still achieving a nominal
output swing of 800 mV. At low data rates, substantial power
savings can be achieved by using lower output swings and higher
load resistances.
AD8151
V
EE
R
SET
REF
V
CC
I
OUT
/20
1.2V
Figure 14. Simplified Reference Circuit
The nominal output current is given by the following expression:
I
V
R
OUT
SET
=
20
1 2
The minimum set resistor is R
SET,MIN
= 960
resulting in
I
OUT,MAX
= 25 mA. The maximum set resistor is R
SET,MAX
=
4.8 k
resulting in I
OUT,MIN
= 5 mA. Nominal 800 mV differen-
tial output swing can be achieved in a 50
load using R
SET
=
1.5 k
(I
OUT
= 16 mA), or in a doubly-terminated 75
load
using R
SET
= 1.13 k
(I
OUT
= 21.3 mA).
To minimize stray capacitance and avoid the pickup of unwanted
signals, the external set resistor should be located close to the
REF pin. Bypassing the set resistor is not recommended.
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參數描述
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