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參數(shù)資料
| 型號(hào)： | AD8151AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 33 x 17, 3.2 Gb/s Digital Crosspoint Switch |
| 中文描述： | 7-BIT, DSP-CROSSBAR SWITCH, PQFP184 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-184 |
| 文件頁(yè)數(shù)： | 16/36頁(yè) |
| 文件大小： | 5326K |
| 代理商： | AD8151AST |
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AD8151
–16–
REV. 0
UPDATE
7
0
1
2
16
33
1 OF 33
DECODERS
1 OF 17 DECODERS
WE
D[0:6]
RE
A[0:4]
RANK 1
17 RLATCHES
RANK 2
RESET
SWITCH
MATRIX
7
33
7
33
7
33
7
7
7
7
0
1
2
16
7
7
7
7
7
7
7
7
7
Figure 8. Control Interface (Simplified Schematic)
AD8151 CONTROL INTERFACE
The AD8151 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
one row for each output. The 7-bit data word stored in each
of these latches indicates to which (if any) of the 33 inputs the
output will be connected.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into
the second rank of latches, and do not change until the first rank
of data is passed into the second rank.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid
output bus contention on system start-up. The contents of the
first rank remain unchanged.
The control interface pins are connected via logic-level transla-
tors. These translators allow programming and readback of the
control interface using logic levels different from those in the
signal matrix.
In order to facilitate multiple chip address decoding, there is a
chip-select pin. All logic signals except the reset pulse are ignored
unless the chip select pin is active. The chip select pin disables
only the control logic interface, and does not change the opera-
tion of the signal matrix. The chip select pin does not power
down any of the latches, so any data programmed in the latches
is preserved.
All control pins are level-sensitive, not edge-triggered.
CONTROL PIN DESCRIPTION
A[4:0] Inputs
Output address pins. The binary encoded address applied to
these five input pins determines which one of the seventeen
outputs is being programmed (or being read back). The most
significant bit is A4.
D[6:0] Inputs/Outputs
Input configuration data pins. In write mode, the binary encoded
data applied to pins D[6:0] determine which one of 33 inputs is
to be connected to the output specified with the A[4:0] pins.
The most significant bit is D5, and the least significant bit is
D0. Bit D6 is the enable bit, setting the specified output sig-
nal pair to an enabled state if D6 is logic HIGH, or disabled
to a high-impedance state if D6 is logic LOW.
In readback mode, pins D[6:0] are low-impedance outputs indi-
cating the data word stored in the second rank for the output
specified with the A[4:0] pins. The readback drivers were designed
to drive high impedances only, so external drivers connected
to the D[6:0] should be disabled during readback mode.
WE
Input
First Rank Write Enable. Forcing this pin to logic LOW allows
the data on pins D[6:0] to be stored in the first rank latch for
the output specified by pins A[4:0]. The
WE
pin must be returned
to a logic HIGH state after a write cycle to avoid overwriting
the first rank data.
UPDATE
Input
Second Rank Write Enable. Forcing this pin to logic LOW allows
the data stored in all 17 first rank latches to be transferred to the
second rank latches. The signal connection matrix will be repro-
grammed when the second rank data is changed. This is a global
pin, transferring all 17 rows of data at once. It is not necessary
to program the address pins. It should be noted that after initial
power-up of the device, the first rank data is undefined. It may
be desirable to preprogram all seventeen outputs before performing
the first update cycle.
RE
Input
Second Rank Read-Enable. Forcing this pin to logic LOW enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address with
the A[4:0] pins and forcing
RE
to logic LOW, the 7-bit data
stored in the second rank latch for that output address will be
written to D[6:0] pins. Data should not be written to the D[6:0]
pins externally while in readback mode. The
RE
and
WE
pins
are not exclusive, and may be used at the same time, but data
should not be written to the D[6:0] pins from external sources
while in readback mode.
CS
Input
Chip-Select. This pin must be forced to logic LOW in order
to program or receive data from the logic interface, with the
exception of the
RESET
pin, described below. This pin has
no effect on the signal pairs and does not alter any of the stored
control data.
RESET
Input
Global Output Disable Pin. Forcing the
RESET
pin to logic
LOW will reset the enable bit, D6, in all 17 second rank
latches, regardless of the state of any other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
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