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參數(shù)資料
| 型號(hào)： | AD8186 |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| 中文描述： | TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大?。?/td> | 474K |
| 代理商： | AD8186 |
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REV. A
–12–
AD8186/AD8187
THEORY OF OPERATION
The AD8186 (G = +1) and AD8187 (G = +2) are single-supply,
triple 2:1 multiplexers with TTL compatible global
input switch-
ing and output-enable control. Optimized for select
ing between
two RGB (red, green, blue) video sources, the devices have high
peak slew rates, maintaining their bandwidth for large signals.
Additionally, the multiplexers are compensated for high phase
margin, minimizing overshoot for good pixel resolution. The
multiplexers also have respectable video specifications and are
superior for switching NTSC or PAL composite signals.
The multiplexers are organized as three independent channels,
each with two input transconductance stages and one output
transimpedance stage. The appropriate input transconductance
stages are selected via one logic pin (SEL A/
B
) such that all
three outputs switch input connections simultaneously. The
unused input stages are disabled with a proprietary clamp cir-
cuit to provide excellent crosstalk isolation between “on” and
“off” inputs while protecting the disabled devices from damag-
ing reverse base-emitter voltage stress. No additional input
buffering is necessary, resulting in low input capacitance and
high input impedance without additional signal degradation.
The transconductance stage, a high slew rate, class AB circuit,
sources signal current into a high impedance node. Each output
stage contains a compensation network and is buffered to the
output by a complementary emitter-follower stage. Voltage
feedback sets the gain, with the AD8186 configured as a unity
gain follower and the AD8187 as a gain-of-two amplifier with a
feedback network. This architecture provides drive for a reverse-
terminated video load (150 ) with low differential gain and
phase errors while consuming relatively little power. Careful
chip layout and biasing result in excellent crosstalk isolation
between channels.
High Impedance, Output Disable Feature, and Off Isolation
The output-enable logic pin (OE) controls whether the three
outputs are enabled or disabled to a high impedance state.
The high impedance disable allows larger matrices to be built
by busing the outputs together. In the case of the AD8187
(G = +2), a feedback isolation scheme is used so that the
impedance of the gain-of-two feedback network does not load
the output. When not in use, the outputs can be disabled to
reduce power consumption.
The reader may have noticed that the off isolation performance of
the signal path is dependent upon the value of the load resistor,
R
L
. For calculating off isolation, the signal path may be modeled
as a simple high-pass network with an effective capacitance of
3 fF. Off isolation will improve as the load resistance is decreased. In
the case of the AD8186, off isolation is specified with a 1 k
load. However, a practical application would likely gang the
outputs of multiple muxes. In this case, the proper load resistance
for the off isolation calculation is the output impedance of an
enabled AD8186, typically less than a 10th of an ohm.
Full Power Bandwidth vs. –3 dB Large Signal Bandwidth
Note that full power bandwidth for an undistorted sinusoidal signal
is often calculated using the peak slew rate from the equation
Full Power Bandwidth =
Peak Slew Rate
Sinusoid Amplitude
2
π ×
The peak slew rate is not the same as the average slew rate. The
average slew rate is typically specified as the ratio
V
t
OUT
measured between the 20% to 80% output levels of a suffi-
ciently large output pulse. For a natural response, the peak slew
rate may be 2.7 times larger than the average slew rate. There-
fore, calculating a full power bandwidth with a specified average
slew rate will give a pessimistic result. In specifying the large
signal performance of these multiplexers, we’ve published the
large-signal bandwidth, the average slew rate, and the measure-
ments of the total harmonic distortion. (Large signal bandwidth
is defined as the –3 dB point measured on a 2 V p-p output
sine wave.) Specifying these three aspects of the signal path’s
large signal dynamics allows the user to predict system behavior
for either pulse or sinusoid waveforms.
Single-Supply Considerations
DC-Coupled Inputs, Integrated Reference Buffers, and
Selecting the V
REF
Level on the AD8187, (G = +2)
The AD8186 and AD8187 offer superior large signal dynamics.
The trade-off is that the input and output compliance is limited
to ~1.3 V from either rail when driving a 150 load. These
sections address some challenges of designing video systems
within a single 5 V supply.
The AD8186
The AD8186 is internally wired as a unity-gain follower. Its
inputs and outputs can both swing to within ~1.3 V of either
rail. This affords the user 2.4 V of dynamic range at input and
output, which should be enough for most video signals, whether
the inputs are ac- or dc-coupled. In both cases, the choice of
output termination voltage will determine the quiescent load
current.
For improved supply rejection, the V
REF
pin should be tied to
an ac ground (the more quiet supply is a good bet). Internally,
the V
REF
pin connects to one terminal of an on-chip capacitor.
The capacitor’s other terminal connects to an internal node.
The consequence of building this bypass capacitor on-chip is
twofold. First, the V
REF
pin on the AD8186 draws no input bias
current. (Contrast this to the case of the AD8187, where the
V
REF
pin typically draws 2
μ
A of input bias current). Second,
on the AD8186, the V
REF
pin may be tied to any voltage within
the supply range.
IN0A
IN0B
IN1B
IN1A
IN2A
IN2B
AD8186
OUT0
OUT1
OUT2
MUX SYSTEM
BIAS REFERENCE
INTERNAL CAP
“C_BYPASS”
DIRECT CONNECTION TO ANY “QUIET” AC GROUND
(FOR EXAMPLE, GND, V
CC
, V
EE)
V
REF
Figure 3. V
REF
Pin Connection for AD8186 (Differs
from AD8187)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8187 | 480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| AD8188ARUZ-RL | 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| AD8188Z-EVALZ | 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| AD8189 | 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| AD8189ARUZ | 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8186ARU | 制造商:Analog Devices 功能描述:Analog Multiplexer Triple 2:1 24-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:TSSOP TRIPLE 2:1 G=+1 SINGLE SUPPLY MUX - Bulk 制造商:Analog Devices 功能描述:Multiplexer IC Multiplexer Type:Multiple |
| AD8186ARU-REEL | 制造商:Analog Devices 功能描述:Analog Multiplexer Triple 2:1 24-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD8186ARU-REEL7 | 制造商:Analog Devices 功能描述:Analog Multiplexer Triple 2:1 24-Pin TSSOP T/R |
| AD8186ARUZ | 功能描述:IC MULTIPLEXER TRPL 2X1 24TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 應(yīng)用說(shuō)明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開(kāi)關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤(pán) |
| AD8186ARUZ-R7 | 功能描述:IC MULTIPLEXER TRPL 2X1 24TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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