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參數(shù)資料
型號(hào): AD8186
廠商: ANALOG DEVICES INC
元件分類: 運(yùn)動(dòng)控制電子
英文描述: 480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers
中文描述: TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO24
封裝: TSSOP-24
文件頁(yè)數(shù): 14/20頁(yè)
文件大小: 474K
代理商: AD8186
REV. A
–14–
AD8186/AD8187
AC-Coupled Inputs (DC Restore before Mux Input)
Using ac-coupled inputs presents an interesting challenge for video
systems operating from a single 5 V supply. In NTSC and PAL
video systems, 700 mV is the approximate difference between the
maximum signal voltage and black level. It is assumed that sync
has been stripped. However, given the two pathological cases
shown in Figure 7, a dynamic range of twice the maximum signal
swing is required if the inputs are to be ac-coupled. A possible
solution would be to use a dc restore circuit before the mux.
V
REF
BLACK LINE WITH WHITE PIXEL
+700mV
V
AVG
+5 V
V
SIGNAL
GND
V
INPUT
= V
REF
+ V
SIGNAL
V
REF
~ V
AVG
V
REF
IS A DC VOLTAGE
SET BY THE RESISTORS
–700mV
WHITE LINE WITH BLACK PIXEL
V
AVG
V
REF
Figure 7. Pathological Case for
Input Dynamic Range
Tolerance to Capacitive Load
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance of
R
EFF
=
(
R
L
r
O
), where
R
L
is the discrete resistive load, and
r
O
is the open-
loop output impedance, approximately 15
for these muxes.
The load pole, at
f
LOAD
= 1/(2
R
EFF
C
L
), can seriously degrade
phase margin and therefore stability. The old workaround is to
place a small series resistance directly at the output to isolate the
load pole. While effective, this ruse also affects the dc and termina-
tion characteristics of a 75
system. The AD8186 and AD8187
are built with a variable compensation scheme that senses the
output reactance and trades bandwidth for phase margin, ensuring
faster settling and lower overshoot at higher capacitive loads.
Secondary Supplies and Supply Bypassing
The high current output transistors are given their own supply
pins (Pins 15, 17, 19, and 21) to reduce supply noise on-chip
and to improve output isolation. Since these secondary, high
current supply pins are not connected on-chip to the primary
analog supplies (V
CC
/V
EE
, Pins 6, 7, 9, 11, 13, and 24), some
care should be taken to ensure that the supply bypass capacitors
are connected to the correct pins. At a minimum, the primary
supplies should be bypassed. Pin 6 and Pin 7 may be a convenient
place to accomplish this. Stacked power and ground planes could
be a convenient way to bypass the high current supply pins.
IN0A
D
GND
V
REF
OUT 0
OUT 1
OUT 2
IN1A
IN2A
IN2B
IN1B
IN0B
V
CC
V
EE
V
EE
V
EE
V
CC
OE
SEL A/
B
V
EE
V
CC
V
CC
V
CC
V
EE
DV
CC
MUX0
MUX1
MUX2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1 F
0.1 F
Figure 8. Detail of Primary and Secondary Supplies
Split-Supply Operation
Operating from split supplies (e.g., +3 V/–2 V or
±
2.5 V) simpli-
fies the selection of the V
REF
voltage and load resistor termination
voltage.
In this case, it is convenient to tie V
REF
to ground.
The logic
inputs are level shifted internally to allow the digital
supplies and
logic inputs to operate from 0 V and 5 V when
powering the
analog circuits from split supplies. The maximum
voltage difference between DV
CC
and V
EE
must not exceed 8 V
(see Figure 9).
DV
CC
(+5)
D
GND
SPLIT-SUPPLY OPERATION
DIGITAL SUPPLIES
(0V)
8V MAX
ANALOG SUPPLIES
(+2.5)
(–2.5)
V
CC
V
EE
Figure 9. Split-Supply Operation
相關(guān)PDF資料
PDF描述
AD8187 480 MHz Single-Supply (5 V) Triple 2:1 Multiplexers
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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