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參數資料
| 型號： | AD8189ARUZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| 中文描述： | TRIPLE 1-CHANNEL, VIDEO MULTIPLEXER, PDSO24 |
| 封裝： | LEAD FREE, MO-153AD, TSSOP-24 |
| 文件頁數： | 16/24頁 |
| 文件大小： | 725K |
| 代理商： | AD8189ARUZ-R7 |
AD8188/AD8189
Rev. 0 | Page 16 of 24
V
REF
5V
10k
10k
1μF
CAP MUST BE LARGE
ENOUGH TO ABSORB
TRANSIENT CURRENTS
WITH MINIMUM BOUNCE.
0
Figure 49. Alternate Method for Synthesis of a False Ground Reference
AC-COUPLED INPUTS
Using ac-coupled inputs presents an interesting challenge for
video systems operating from a single 5 V supply. In NTSC and
PAL video systems, 700 mV is the approximate difference
between the maximum signal voltage and black level. It is
assumed that sync has been stripped. However, given the two
pathological cases shown in Figure 50, a dynamic range of twice
the maximum signal swing is required if the inputs are to be
ac-coupled. A possible solution is to use a dc restore circuit
before the mux.
+700mV
–700mV
+5V
GND
V
AVG
V
AVG
V
SIGNAL
V
REF
V
REF
WHITE LINE WITH BLACK PIXEL
BLACK LINE WITH WHITE PIXEL
V
INPUT
= V
REF
+ V
SIGNAL
V
REF
~ V
V
IS A DC VOLTAGE
SET BY THE RESISTORS
0
Figure 50. Pathological Case for Input Dynamic Range
TOLERANCE TO CAPACITIVE LOAD
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance (R
EFF
) of
R
EFF
= (
R
L
||
r
O
)
where
R
L
is the discrete resistive load, and
r
O
is the open loop
output impedance, approximately 15 Ω for these muxes.
The load pole (f
LOAD
) at
1
L
EFF
LOAD
C
R
f
π
=
2
can seriously degrade phase margin and, therefore, stability. The
old workaround is to place a small series resistor directly at the
output to isolate the load pole. While effective, this ruse also
affects the dc and termination characteristics of a 75 Ω system.
The AD8188 and AD8189 are built with a variable compensation
scheme that senses the output reactance and trades bandwidth
for phase margin, ensuring faster settling and lower overshoot
at higher capacitive loads.
SECONDARY SUPPLIES AND SUPPLY BYPASSING
The high current output transistors are given their own supply
pins (Pin 15, Pin 17, Pin 19, and Pin 21) to reduce supply noise
on-chip and to improve output isolation. Because these
secondary, high current supply pins are not connected on-chip
to the primary analog supplies, V
CC
/V
EE
(Pin 6, Pin 7, Pin 9,
Pin 11, Pin 13, and Pin 24), some care should be taken to ensure
that the supply bypass capacitors are connected to the correct
pins. At a minimum, the primary supplies should be bypassed.
Pin 6 and Pin 7 can be a convenient place to accomplish this.
Stacked power and ground planes are a convenient way to
bypass the high current supply pins (see Figure 51).
MUX1
MUX2
MUX3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
0.1μF
1μF
V
CC
V
CC
DV
CC
V
EE
OUT2
V
CC
OUT1
V
EE
OUT0
V
CC
OE
IN0A
IN0B
V
EE
IN1B
V
EE
IN2B
V
EE
V
CC
IN2A
V
REF
IN1A
D
GND
SEL A/B
0
Figure 51. Detail of Primary and Secondary Supplies
SPLIT-SUPPLY OPERATION
Operating from split supplies (for example, [+3 V/2 V] or
±2.5 V) simplifies the selection of the V
REF
voltage and load
resistor termination voltage. In this case, it is convenient to tie
V
REF
to ground. The logic inputs are internally level-shifted to
allow the digital supplies and logic inputs to operate from 0 V
and 5 V when powering the analog circuits from split supplies.
The maximum voltage difference between DV
CC
and V
EE
must
not exceed 8 V (see Figure 52).
8V MAX
(+5V)
(0V)
(+2.5V)
(–2.5V)
DV
CC
D
GND
V
CC
V
EE
DIGITAL SUPPLIES
ANALOG SUPPLIES
0
Figure 52. Split-Supply Operation
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