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參數資料
| 型號： | AD824BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp |
| 中文描述： | QUAD OP-AMP, 2500 uV OFFSET-MAX, 2 MHz BAND WIDTH, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數： | 14/16頁 |
| 文件大小： | 551K |
| 代理商： | AD824BN |
AD824
–14–
REV. A
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing a JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1
μ
V/
μ
s in this circuit. Higher values of C
H
will yield a lower
droop rate. For best performance, C
H
and C2 should be poly-
styrene, polypropylene or Teflon capacitors. These types of
capacitors exhibit low leakage and low dielectric absorption. Addi-
tionally, 1% metal film resistors were used throughout the design.
In the sample mode, SW1 and SW4 are closed, and the output
is V
OUT
= –V
IN
. The purpose of SW4, which operates in paral-
lel with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting input
of A3 that SW1 injects into the inverting input of A3. This cre-
ates a common-mode voltage across the inputs of A3 and is then
rejected by the CMR of A3; otherwise, the charge injection from
SW1 would create a differential voltage step error that would
appear at V
OUT
. The pedestal error for this circuit is less than 2
mV over the entire 0 V to 3.3 V/5 V signal range. Another
method of reducing pedestal error is to reduce the pulse ampli-
tude applied to the control pins. In order to control the
ADG513, only 2.4 V are required for the “ON” state and 0.8V
for the “OFF” state. If possible, use an input control signal
whose amplitude ranges from 0.8 V to 2.4 V instead of a full
range 0 V to 3.3 V/5 V for minimum pedestal error.
Other circuit features include an acquisition time of less than
3
μ
s to 1%; reducing C
H
and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normally-open and normally-closed pre-
cision CMOS switches on a dielectrically isolated process. SW2
is not required in this circuit; however, it was used in parallel
with SW3 to provide a lower R
ON
analog switch.
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