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參數(shù)資料
| 型號(hào)： | AD8302 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LF.2.7 GHz RF/IF Gain and Phase Detector |
| 中文描述： | LF.2.7 GHz射頻/中頻增益和相位檢波器 |
| 文件頁(yè)數(shù)： | 16/24頁(yè) |
| 文件大小： | 533K |
| 代理商： | AD8302 |
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REV. 0
AD8302
–16–
Note that by convention, the phase difference is taken in the range
from –180
°
to +180
°
. Since this style of phase detector does not
distinguish between
±
90
°
it is considered to have an unambiguous
180
°
phase difference range which can be either 0
°
to +180
°
cen-
tered at 90
°
, or 0
°
to –180
°
centered at –90
°
.
The basic structure of both output interfaces is shown in Figure 3. It
accepts a setpoint input and includes an internal integrating/averag-
ing capacitor and a buffer amplifier with gain K. External access to
these setpoints provides for several modes of operation and enables
flexible tailoring of the gain and phase transfer characteristics. The
setpoint interface block, characterized by a transresistance R
F
, gener-
ates a current proportional the voltage presented to its input pin,
MSET or PSET. A precise offset voltage of 900 mV is introduced
internally to establish the center-point (V
CP
) for the gain and phase
functions; i.e., the setpoint voltage that corresponds to a gain of 0 dB
and a phase difference of 90
°
. This setpoint current is subtracted
from the signal current, I
IN
, coming from the log amps in the gain
channel or from the phase detector in the phase channel. The result-
ing difference is integrated on the averaging capacitors at either pin
MFLT or PFLT and then buffered by the output amplifier to the
respective output pins, VMAG and VPHS. With this open-loop
arrangement, the output voltage is a simple integration of the differ-
ence between the measured gain/phase and the desired setpoint,
V
OUT
=
R
F
(
I
IN
–
I
FB
)/(
sT
),
where
I
FB
is the feedback current equal to (
V
SET
–V
CP
)/
R
F
,
V
SET
is the
setpoint input and
T
is integration time constant equal to R
F
C
AVE
/K,
where C
AVE
is the parallel combination of the internal 1.5 pF and the
external capacitor C
FLT
.
(6)
K
R
F
MSET/PSET
20k
+
+
V
CP
= 900mV
1.5pF
C
FLT
MFLT/PFLT
VMAG/VPHS
I
IN
= I
LA
OR
I
PD
I
FB
+
–
Figure 3. Simplified Block Diagram of the Output Interface
BASIC CONNECTIONS
Measurement Mode
The basic function of the AD8302 is the direct measurement of gain
and phase. When the output pins, VMAG and VPHS, are connected
directly to the feedback setpoint input pins, MSET and PSET, the
default slopes and center-points are invoked. This basic connection
shown in Figure 4 is termed the measurement mode. The current
from the setpoint interface is forced by the integrator to be equal to
the signal currents coming from the log amps and phase detector.
The closed loop transfer function is thus given by
V
OUT
= (
I
IN
R
F
+
V
CP
)/(1+
sT
).
The time constant
T
represents the single-pole response to the enve-
lope of the dB-scaled gain and the degree-scaled phase functions. A
small internal capacitor sets the maximum envelope bandwidth to
approximately 30 MHz. If no external C
FLT
is used, the AD8302
can follow the gain and phase envelopes within this bandwidth. If
longer averaging is desired, C
FLT
can be added as necessary accord-
ing to T (ns) = 3.3
×
C
AVE
(pF). For best transient response with
minimal overshoot, it is recommended that 1 pF minimum value
external capacitors be added to the MFLT and PFLT pins.
(7)
1
COMM
MFLT
14
INPA
VMAG
2
13
OFSA
MSET
3
12
VPOS
VREF
4
11
OFSB
PSET
5
10
INPB
VPHS
6
9
COMM
PFLT
7
8
AD8302
C2
V
MAG
V
PHS
C8
C1
C4
C6
C5
R1
R2
V
INA
V
INB
VP
C7
R4
C3
Figure 4. Basic Connections for the AD8302 in Measurement
Mode with 30 mV/dB and 10 mV/Degree Scaling
In the low frequency limit, the gain and phase transfer functions
given in Equations 4 and 5 become,
V
MAG
= R
F
I
SLP
log (
V
INA
/V
INB
)
+ V
CP
or
V
MAG
= (R
F
I
SLP
/20)
(
P
INA
–P
INB
)
+V
CP
V
PHS
= –R
F
I
Φ
(
|
Φ
(
V
INA
)
–
Φ
(
V
INB
)
|–90
°
)
+ V
CP
which are illustrated in Figure 5. In Equation 8b,
P
INA
and
P
INB
are
the power in dBm equivalent to
V
INA
and
V
INB
at a specified refer-
ence impedance. For the gain function, the slope represented by
R
F
I
SLP
is 600 mV/decade or dividing by 20 dB/decade, 30 mV/dB.
With a center-point of 900 mV for 0 dB gain, a range of –30 dB to
+30 dB covers the full-scale swing from 0 V to 1.8 V. For the phase
function, the slope represented by
R
F
I
Φ
is 10 mV/degree. With a
center-point of 900 mV for 90
°
, a range of 0
°
to +180
°
covers the
full-scale swing from 1.8 V to 0 V. The range of 0
°
to –180
°
covers
the same full-scale swing but with the opposite slope.
(8a)
(8b)
(9)
1.8V
900mV
0V
V
M
V
P
30 mV/dB
V
CP
MAGNITUDE RATIO
–
dB
–
30
0
+30
1.8V
900mV
0V
PHASE DIFFERENCE
–
Degrees
+10 mV/DEG
–
10 mV/DEG
V
CP
–
180
–
90
0
90
180
Figure 5. Idealized Transfer Characteristics for the Gain
and Phase Measurement Mode
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