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參數資料
| 型號： | AD8316-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Output GSM PA Controller |
| 中文描述： | 雙輸出GSM功率放大器控制器 |
| 文件頁數： | 2/20頁 |
| 文件大小： | 497K |
| 代理商： | AD8316-EVAL |
REV. C
–2–
AD8316–SPECIFICATIONS
(V
POS
= 2.7 V, T
A
= 25 C, 52.3 on RFIN, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
1
Input Voltage Range
Equivalent dBm Range
Logarithmic Slope
2, 3
Logarithmic Intercept
2, 3
Equivalent dBm Level
To Meet All Specifications
±
1 dB Log Conformance, 0.1 GHz
0.1
–58.6
–45.6
20.5
–68
–55
2.5
–10
+3
24.5
–78
–65
GHz
dBV
dBm
mV/dB
dBV
dBm
0.1 GHz
0.1 GHz
22.1
–74
–61
RF INPUT INTERFACE
Input Resistance
4
Input Capacitance
4
Pin RFIN
0.1 GHz
0.1 GHz
2.9
1.0
k
pF
OUTPUTS
Minimum Output Voltage
Pins OUT1 and OUT2
VSET
≤
200 mV, ENBL High, RF Input
≤
–60 dBm
ENBL Low
R
L
> 800
2.7 V
≤
V
POS
≤
5.5 V
Source
0.1
0.15
0.025
0.25
V
V
V
V
mA
nV/
√
Hz
nV/
√
Hz
Maximum Output Voltage
General Limit
Output Current Drive
Output Buffer Noise
Output Noise
2.45
2.6
V
POS
– 0.1
12
25
100
RF Input = 2 GHz, 0 dBm,
C
FLT
= 220 pF, f
NOISE
= 400 kHz
0.2 V to 2.6 V Swing
10%–90%, 250 mV Step (V
SET
), Open Loop
5
FLTR = Open; Refer to TPC 28
Small Signal Bandwidth
Slew Rate
Full-Scale Response Time
30
20
50
MHz
V/
μ
s
ns
SETPOINT INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Input Resistance
Slew Rate
Pin VSET
Corresponding to Central 50 dB
0.25
1.5
V
dB/V
k
V/
μ
s
43.5
100
16
ENABLE INTERFACE
Logic Level to Enable Power
Input Current when Enable High
Logic Level to Disable Power
Enable Time
Pin ENBL
1.8
V
POS
V
μ
A
V
μ
s
20
0.8
Time from ENBL High to V
APC
within 1% of
Final Value, C
FLT
= 68 pF; Refer to TPC 20
Time from ENBL Low to V
APC
within 1% of
Final Value, C
FLT
= 68 pF; Refer to TPC 20
Time from VPOS/ENBL Low to V
APC
within
1% of Final Value, C
FLT
= 68 pF; Refer to TPC 25
Time from VPOS/ENBL High to V
APC
within
1% of Final Value, C
FLT
= 68 pF; Refer to TPC 25
7
Disable Time
3
μ
s
Power-On/Enable Time
3
μ
s
Power-Off/Disable Time
4
μ
s
BAND SELECT INTERFACE
Logic Level to Enable OUT1
Input Current when BSEL High
Logic Level to Enable OUT2
Pin BSEL
1.8
V
POS
V
μ
A
V
50
0.0
1.7
POWER INTERFACE
Supply Voltage
Quiescent Current
Over Temperature
Disable Current
6
Over Temperature
Pin VPOS
2.7
5.5
10.7
12
10
13
V
mA
mA
μ
A
μ
A
ENBL High
–30
°
C
≤
T
A
≤
+85
°
C
ENBL Low
–30
°
C
≤
T
A
≤
+85
°
C
8.5
3
NOTES
1
Operation down to 0.02 GHz is possible.
2
Calculated over the input range of –40 dBm to –10 dBm.
3
Mean and standard deviation specifications are in Table I.
4
See TPC 9 for plot of Input Impedance vs. Frequency.
5
Response time in a closed-loop system will depend upon the filter capacitor (C
) used and the response of the variable gain element.
6
This parameter is guaranteed but not tested in production. The maximum specified limit on this parameter is the +6 sigma value from characterization.
Specifications subject to change without notice.
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