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參數(shù)資料
| 型號(hào)： | AD8316-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Output GSM PA Controller |
| 中文描述： | 雙輸出GSM功率放大器控制器 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大小： | 497K |
| 代理商： | AD8316-EVAL |
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REV. C
AD8316
–9–
10mV PER
VERTICAL
DIVISION
2V PER
VERTICAL DIVISION
2 s PER HORIZONTAL DIVISION
V
OUT
AVERAGING = 16 SAMPLES
V
INPUT
250ns
RISE TIME
1 s
RISE TIME
TPC 31. Power-On and Power-Off Response with
VSET and ENBL Grounded
RFOUT
H-P 8648B
SIGNAL
GENERATOR
0.1GHz
–60dBm
52.3
AD8316
OUT2
FLT2
VPOS
OUT1
COMM
FLT1
BSEL
*
RFIN
ENBL
VSET
C
FLT
C
FLT
H-P 8110A
PULSE
GENERATOR
R
L
1k
TEK 1103
PWR SUPPLY
TEK TDS3054
SCOPE
PULSE OUT
*
BSEL HIGH
BSEL LOW
OUT1;
OUT2
AD811
TEK P6204
FET PROBE
732
49.9
TEK P6204
FET PROBE
TPC 32. Test Setup for Power-On and Power-Off
Response with VSET and ENBL Grounded
GENERAL DESCRIPTION AND THEORY
The AD8316 is a wideband logarithmic amplifier (log amp) with
two selectable outputs suitable for dual-band/dual-mode power
amplifier control. It is strictly optimized for power control appli-
cations rather than for use as a measurement device. Figure 1
shows its main features in block schematic form. The output
pins, OUT1 and OUT2, are intended to be applied directly to
the automatic power control (APC) pins of two distinct power
amplifiers. When the band select pin, BSEL, directs one of the
controller outputs to servo its amplifier toward the setpoint
indicated by the power control pin VSET, the other output is
forced to ground, disabling the second amplifier. Each output
has a dedicated filter pin, FLT1 and FLT2, that allows the
filtering and loop dynamics for each control loop to be opti-
mized independently.
Basic Theory
Logarithmic amplifiers provide a type of compression in which a
signal with a large range of amplitudes is converted to one of
a smaller range. The use of the logarithmic function uniquely
results in the output representing the decibel value of the input.
The fundamental mathematical form is
V
V
V
V
OUT
SLP
IN
Z
=
log
(1)
Here
V
IN
is the input voltage and
V
Z
is called the intercept (volt-
age) because when V
IN
= V
Z
the argument of the logarithm is
unity, and thus the result is zero;
V
SLP
is called the slope (volt-
age), which is the amount by which the output changes for a
certain change in the ratio (V
IN
/V
Z
).
Because log amps do not respond to power, but only to voltages,
and the calibration of the intercept is waveform dependent and
only quoted for a sine wave signal, the
equivalent power response
can be written as
=
(
–
)
V
V
P
P
OUT
DB
IN
Z
(2)
where the input power
P
IN
and the equivalent intercept
P
Z
are
both expressed in dBm (thus, the quantity in the parentheses is
simply a number of decibels), and
V
DB
is the slope expressed as
so many mV/dB. When base 10 logarithms are used, denoted by
the function log
10
, V
SLP
represents V/dec, and since a decade
corresponds to 20 dB, V
SLP
/20 represents the change in V/dB. For
the AD8316, a nominal (low frequency) slope of 22 mV/dB
(corresponding to a V
SLP
of 0.022 mV/dB
×
20 dB = 440 mV)
was chosen, and the intercept V
Z
was placed at the equivalent of
–74 dBV, or 199
μ
V rms, for a sine wave input. This corre-
sponds to a power level of –61 dBm when the net resistive part
of the input impedance of the log amp is 50
. However, both
the slope and the intercept are dependent on frequency (see for
example, TPC 13 and TPC 16).
For a log amp with a slope V
DB
of +22 mV/dB and an inter-
cept at –61 dBm, the output voltage for an input power of
–30 dBm is 0.022
×
(–30 – [–61]) = 0.682 V.
OUT2
OUT1
FLT1
VSET
325mV TO
1.4V = 49dB
FLT2
10dB
COMM
OFFSET
COMPENSATION
RFIN
10dB
10dB
10dB
DET
DET
DET
DET
DET
INTERCEPT
POSITIONING
LOW NOISE
GAIN BIAS
LOW NOISE
BAND GAP
REFERENCE
OUTPUT
ENABLE
DELAY
ENBL
VPOS
BSEL
1.35
HI-Z
HI-Z
V–I
LOW NOISE
RAIL-TO-RAIL
BUFFERS
1.35
Figure 1. Block Schematic of the AD8316
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