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參數資料
型號: AD8351-EVAL
廠商: Analog Devices, Inc.
元件分類: 運動控制電子
英文描述: Low Distortion Differential RF/IF Amplifier
中文描述: 低失真差分射頻/中頻放大器
文件頁數: 11/16頁
文件大小: 465K
代理商: AD8351-EVAL
REV. B
AD8351
–11–
200
0
50
150
SERIES L
SHUNT C
500
100
50
25
10
200
100
500
50
25
10
Figure 4. Smith Chart Representation of SAW
Filter Output Matching Network
50
50
AD8351
R
G
0.1 F
25
R
F
0.1 F
0.1 F
R
L
0.1 F
Figure 5. Single-Ended Application
SINGLE-ENDED-TO-DIFFERENTIAL OPERATION
The AD8351 can easily be configured as a single-ended-to-
differential gain block, as illustrated in Figure 5. The input signal
is ac-coupled and applied to the INHI input. The unused input is
ac-coupled to ground. The values of C1 through C4 should be
selected such that their reactances are negligible at the desired
frequency of operation. To balance the outputs, an external feed-
back resistor, R
F
, is required. To select the gain resistor and the
feedback resistor, refer to Figures 6a and 6b. From Figure 6a,
select an R
G
for the required dB gain at a given load. Next, select
from Figure 6b an R
F
resistor for the selected R
G
and load.
Even though the differential balance is not perfect under these
conditions, the distortion performance is still impressive. TPCs 10
and 11 show the second and third harmonic distortion perfor-
mance when driving the input of the AD8351 using a single-ended
50
source.
R
G
( )
0
1000
G
10
0
15
5
35
20
25
30
100
R
L
= 500
R
L
= 1000
R
L
= 150
Figure 6a. Gain Selection
R
G
( )
0
1000
R
F
(
2
0
3
1
7
4
5
6
100
R
L
= 150
R
L
= 1000
R
L
= 500
Figure 6b. Feedback Resistor Selection
ADC DRIVING
The circuit in Figure 7 represents a simplified front end of the
AD8351 driving the AD6645, which is a 14-bit, 105 MSPS A/D
converter. For optimum performance, the AD6645 and the
AD8351 are driven differentially. The resistors R1 and R2 present
a 50
differential input impedance to the source with R3 and R4
providing isolation from the A/D input. The gain setting resistor
for the AD8351 is R
G
. The AD6645 presents a 1 k
differential
load to the AD8351 and requires a 2.2 V p-p differential signal
between AIN and
AIN
for a full-scale output. This AD8351
circuit then provides the gain, isolation, and source matching for
the AD6645. The AD8351 also provides a balanced input, not
provided by the balun, to the AD6645, which is essential for
second-order cancellation. The signal generator is bipolar,
centered around ground. Connecting the VOCM pin (10) of the
AD8351 to the VREF pin of the AD6645 sets the common-mode
output voltage of the AD8351 at 2.4 V. This voltage is bypassed
with a 0.1
μ
F capacitor. Increasing the gain of the AD8351 will
increase the system noise and thus decrease the SNR but will
not significantly affect the distortion. The circuit in Figure 7 can
provide SFDR performance of better than –90 dBc with a 10 MHz
input and –80 dBc with a 70 MHz input at a gain of 10 dB.
BALANCE
50
SOURCE
25
100nF
25
100nF
AD8351
INHI
INLO
R
G
OPHI
OPLO
VOCM
25
25
DIGITAL
OUT
AD6645
AIN
AIN
VREF
Figure 7. ADC Driving Application Using Differential Input
The circuit of Figure 8 represents a single-ended input to differ-
ential output configuration of the AD8351 driving the AD6645.
In this case, R1 provides the input impedance. R
G
is the gain
setting resistor. The resistor R
F
is required to balance the output
voltages required for second-order cancellation by the AD6645
and can be selected using a chart. (See the Single-Ended-to-
Differential Operation section.) The circuit depicted in Figure 8
can provide SFDR performance of better than –90 dBc with a
10 MHz input and –77 dBc with a 70 MHz input.
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