- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373945 > AD8370 (Analog Devices, Inc.) LF to 750 MHz Digitally Controlled VGA PDF資料下載
參數(shù)資料
| 型號(hào)： | AD8370 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | LF to 750 MHz Digitally Controlled VGA |
| 中文描述： | LF到750兆赫數(shù)字控制VGA |
| 文件頁(yè)數(shù)： | 14/28頁(yè) |
| 文件大小： | 1043K |
| 代理商： | AD8370 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
AD8370
OUTPUT AMPLIFIER
The output impedance is approximately 100 differential and,
like the input preamplifier, this impedance is formed using
active circuit elements. See Figure 38 for a simplified schematic
of the output interface.
Rev. 0 | Page 14 of 28
Table 4. Serial Programming Timing Parameters
Parameter
Clock Pulse Width (T
PW
)
Clock Period (T
CK
)
Setup Time Data vs. Clock (T
DS
)
Setup Time Latch vs. Clock (T
ES
)
Hold Time Latch vs. Clock (T
EH
)
Min
25
50
10
20
10
Unit
ns
ns
ns
ns
ns
VCC/2
740
OPHI/OPLO
0
10
μ
A
CLCK/DATA/LTCH/PWUP
0
Figure 38. OPHI/OPLO Simplified Circuit
Figure 40. Simplified Circuit for Digital Inputs
The gain of the output amplifier, and thus the AD8370 as a
whole, is load dependent. The following equation can be used to
predict the gain deviation of the AD8370 from that at 100 as
the load is varied:
VCC/2
75
VOCM
0
LOAD
R
ion
GainDeviat
98
1
98
.
+
=
For example, if
R
LOAD
is 1 k, the gain is a factor of 1.80 (5.12 dB)
above
that at 100 , all other things being equal. If
R
LOAD
is 50 ,
the gain is a factor of 0.669 (3.49 dB)
below
that at 100 .
Figure 41. Simplified Circuit for VOCM Output
DIGITAL INTERFACE AND TIMING
The digital control port uses a standard TTL interface. The 8-bit
control word is read in a serial fashion when the LTCH pin is
held low. The levels presented to the DATA pin are read on each
rising edge of the CLCK signal. Figure 39 illustrates the timing
diagram for the control interface. Minimum values for timing
parameters are presented in Table 4. Figure 40 is a simplified
schematic of the digital input pins.
DATA
(Pin 14)
CLCK
(Pin 13)
LTCH
(Pin 12)
T
DS
T
ES
T
EH
MSB
MSB-1 MSB-2 MSB-3
LSB
LSB+1
LSB+2
LSB+3
T
CK
T
PW
0
Figure 39. Digital Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8370-EVAL | LF to 750 MHz Digitally Controlled VGA |
| AD8370ARE | LF to 750 MHz Digitally Controlled VGA |
| AD8370ARE-REEL7 | LF to 750 MHz Digitally Controlled VGA |
| AD8383 | Low Cost 10-Bit, 6-Channel Output Decimating LCD DecDriver |
| AD8383ACPZ | Low Cost 10-Bit, 6-Channel Output Decimating LCD DecDriver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8370_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LF to 750 MHz, Digitally Controlled VGA |
| AD8370ARE | 制造商:Analog Devices 功能描述:SP Amp Variable Gain Amp Single 5.5V 16-Pin TSSOP EP Tube 制造商:Analog Devices 功能描述:SP AMP VARIABLE GAIN AMP SGL 5.5V 16TSSOP - Rail/Tube 制造商:Analog Devices 功能描述:IC AMP VARIABLE GAIN |
| AD8370ARE-REEL7 | 功能描述:IC AMP VGA DIFF LN 16TSSOP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 放大器類型:音頻 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:5 V/µs 增益帶寬積:12MHz -3db帶寬:- 電流 - 輸入偏壓:100nA 電壓 - 輸入偏移:500µV 電流 - 電源:6mA 電流 - 輸出 / 通道:50mA 電壓 - 電源，單路/雙路(±):4 V ~ 32 V，±2 V ~ 16 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| AD8370AREZ | 功能描述:IC AMP VGA DIFF LN 16TSSOP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| AD8370AREZ | 制造商:Analog Devices 功能描述:IC VARIABLE GAIN AMP 750MHZ TSSOP-16 制造商:Analog Devices 功能描述:IC, VARIABLE GAIN AMP, 750MHZ, TSSOP-16 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。