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參數資料
| 型號： | AD8392ACP-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver |
| 中文描述： | QUAD OP-AMP, 5000 uV OFFSET-MAX, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD, LFCSP-32 |
| 文件頁數： | 8/16頁 |
| 文件大小： | 529K |
| 代理商： | AD8392ACP-R2 |
AD8392
Rev. 0 | Page 8 of 16
–10
–8
–6
–4
–2
0
2
4
6
8
10
TIME (
μ
s)
0
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
O
Figure 16. Small Signal Pulse Response
Quad Op Amp Circuit (Figure 29)
V
S
= ±12 V, R
LOAD
= 100 , G = +5, 100 mV Step
0
CH1
200mV
CH2 1.00mV
M 50.0ns
A CH2 2.38V
2
1
BW
BW
OUTPUT
PD PINS
Figure 17. Power-Up Time: PD (1, 1) to PD (0, 0)
Quad Op Amp Circuit (Figure 29)
V
S
= ±12 V, R
LOAD
= 100 , G = +5, V
OUT
= 1 V p-p
0
CH1
5.00V
CH2 5.00V
M1.00
μ
s
CH1 700mV
2
1
OUTPUT
INPUT
: 460ns
@: –1.32
μ
s
C1 p-p
27.0V
C2 p-p
21.4V
Figure 18. Input Overdrive Recovery
Quad Op Amp Circuit (Figure 29)
V
S
= ±12 V, R
LOAD
= 100 , G = +1, V
IN
= 27 V p-p
–10
–8
–6
–4
–2
0
2
4
6
8
10
TIME (
μ
s)
0
O
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
Figure 19. Large Signal Pulse Response
Quad Op Amp Circuit (Figure 29)
V
S
= ±12 V, R
LOAD
= 100 , G = +5, 4 V Step
0
CH1
200mV
BW
CH2 1.00V
BW
M 400ns
CH2 2.38V
2
1
OUTPUT
PD PINS
Figure 20. Power-Down Time: PD (0, 0) to PD (1, 1)
Quad Op Amp Circuit (Figure 29)
V
S
= ±12 V, R
LOAD
= 100 , G = +5, V
OUT
= 1 V p-p
0
CH1
1.00V
CH2 5.00V
M1.00
μ
s
CH1 800mV
2
1
OUTPUT
INPUT
: 420ns
@: 2.84
μ
s
C1 p-p
6.00V
C2 p-p
21.8V
Figure 21. Output Overdrive Recovery
Quad Op Amp Circuit (Figure 29)
V
S
= ±12 V, R
LOAD
= 100 , G = +5, V
IN
= 6 V p-p
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