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參數(shù)資料
| 型號： | AD8400AR100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 496K |
| 代理商： | AD8400AR100 |
All VERSIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
SWITCHING CHARACTERISTICS
2, 3
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
4
CS
Setup Time
CS
High Pulse Width
Reset Pulse Width
CLK Fall to
CS
Rise Hold Time
CS
Rise to Clock Rise Setup
t
CH
, t
CL
t
DS
t
DH
t
PD
t
CSS
t
CSW
t
RS
t
CSH
t
CS1
Clock Level High or Low
10
5
5
1
10
10
50
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L
= 1 k
to +5 V, C
L
≤
20 pF
25
NOTES
1
Typicals represent average readings at +25
°
C and V
= +5 V.
2
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
3
See timing diagram for location of measured values. All input control voltages are specified with t
= t
= 1 ns (10% to 90% of V
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using V
= +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/
μ
s should be maintained.
4
Propagation Delay depends on value of V
DD
, R
L
and C
L
–see applications text.
Specifications subject to change without notice.
AD8400/AD8402/AD8403–SPECIFICATIONS
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8400/AD8402/AD8403 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
(V
DD
= +3 V
6
10% or + 5 V
6
10%, V
A
= +V
DD
, V
B
= 0 V, –40
8
C
≤
T
A
≤
+85
8
C unless
otherwise noted)
DAC REGISTER LOAD
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
V
DD
0V
SDI
CLK
CS
V
OUT
Figure 1a. Timing Diagram
±
1 % ERROR BAND
±
1 %
t
CSH
t
CSS
t
DH
Ax OR Dx
Ax OR Dx
t
PD_MIN
t
PD_MAX
A'x OR D'x
A'x OR D'x
1
0
1
0
1
0
V
DD
0V
SDI
(DATA IN)
CLK
CS
V
OUT
1
0
SDO
(DATA OUT)
t
DS
t
CH
t
CS1
t
CL
t
S
t
CSW
Figure 1b. Detail Timing Diagram
±
1%
±
1% ERROR BAND
RS
1
0
V
DD
V
DD
/2
V
OUT
t
RS
t
S
Figure 1c. Reset Timing Diagram
–5–
REV. B
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
°
C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
A
X
–B
X
, A
X
–W
X
, B
X
–W
X
. . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40
°
C to +85
°
C
Maximum Junction Temperature (T
J
max) . . . . . . . . . +150
°
C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300
°
C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/
θ
JA
Thermal Resistance
(θ
JA
)
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83
°
C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63
°
C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70
°
C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120
°
C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180
°
C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143
°
C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
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