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參數(shù)資料
| 型號： | AD8400AR100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 496K |
| 代理商： | AD8400AR100 |
AD8400/AD8402/AD8403
REV. B
–7–
AD8400 PIN DESCRIPTIONS
Pin
Name
Description
1
2
3
B1
GND
CS
Terminal B RDAC
Ground
Chip Select Input, Active Low. When
CS
returns high data in the serial input register is
loaded into the DAC register.
Serial Data Input
Serial Clock Input, positive edge triggered
Positive power supply, specified for operation
at both +3 V and +5 V.
Wiper RDAC, addr = 00
2
Terminal A RDAC
4
5
6
SDI
CLK
V
DD
7
8
W1
A1
AD8402 PIN DESCRIPTIONS
Pin
Name
Description
1
2
3
4
5
6
AGND
B2
A2
W2
DGND
SHDN
Analog Ground*
Terminal B RDAC #2
Terminal A RDAC #2
Wiper RDAC #2, Addr = 01
2
Digital Ground*
Terminal A open circuit. Shutdown controls
Variable Resistors #1 and #2
Chip Select Input, Active Low. When
CS
returns high data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register.
Serial Data Input
Serial Clock Input, positive edge triggered
Active low reset to midscale; sets RDAC
registers to 80
H
Positive power supply, specified for operation
at both +3 V and +5 V
Wiper RDAC #1, addr = 00
2
Terminal A RDAC #1
Terminal B RDAC #1
7
CS
8
9
10
SDI
CLK
RS
11
V
DD
12
13
14
W1
A1
B1
*All AGNDs must be connected to DGND.
AD8403 PIN DESCRIPTIONS
Pin
Name
Description
1
2
3
4
5
6
7
8
9
10
AGND2
B2
A2
W2
AGND4
B4
A4
W4
DGND
SHDN
Analog Ground #2*
Terminal B RDAC #2
Terminal A RDAC #2
Wiper RDAC #2, addr = 01
2
Analog Ground #4*
Terminal B RDAC #4
Terminal A RDAC #4
Wiper RDAC #4, addr = 11
2
Digital Ground*
Active Low Input. Terminal A open circuit.
Shutdown controls variable resistors #1
through #4
Chip Select Input, Active Low. When
CS
returns high data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
Serial Data Input
Serial Data Output, Open Drain transistor
requires pull-up resistor
Serial Clock Input, positive edge triggered
Active low reset to midscale; sets RDAC
registers to 80
H
Positive power supply, specified for
operation at both +3 V and +5 V
Analog Ground #3*
Wiper RDAC #3, addr = 10
2
Terminal A RDAC #3
Terminal B RDAC #3
Analog Ground #1*
Wiper RDAC #1, addr = 00
2
Terminal A RDAC #1
Terminal B RDAC #1
11
CS
12
13
SDI
SDO
14
15
CLK
RS
16
V
DD
17
18
19
20
21
22
23
24
AGND3
W3
A3
B3
AGND1
W1
A1
B1
*All AGNDs must be connected to DGND.
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