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參數資料
| 型號： | AD8402 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數字電位計 |
| 英文描述： | 2-Channel, 256-Position Digital Potentiometer |
| 中文描述： | 2通道，256位數字電位器 |
| 文件頁數： | 14/20頁 |
| 文件大小： | 496K |
| 代理商： | AD8402 |
AD8400/AD8402/AD8403
–14–
REV. B
Table II. Input Logic Control Truth Table
CLK
CS
RS
SHDN
Register Activity
L
P
L
L
H
H
H
H
No SR effect, enables SDO pin.
Shift One bit in from the SDI pin.
The tenth previously entered bit is
shifted out of the SDO pin.
Load SR data into RDAC latch
based on A1, A0 decode (Table III).
No Operation.
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared.
Latches all RDAC latches to 80
H
.
Open circuits all resistor
A–terminals, connects W to B,
turns off SDO output transistor.
X
P
H
H
X
X
H
X
H
L
H
H
X
X
H
H
P
H
H
L
NOTE: P = positive edge, X = don’t care, SR = shift register.
The serial data-output (SDO) pin contains an open drain n-
channel FET. This output requires a pull-up resistor in order to
transfer data to the next package’s SDI pin. The pull-up resistor
termination voltage may be larger than the V
DD
supply (but less
than max V
DD
of +8 V) of the AD8403 SDO output device,
e.g., the AD8403 could operate at V
DD
= 3.3 V and the pull-up
for interface to the next device could be set at +5 V. This allows
for daisy chaining several RDACs from a single processor serial
data line. The clock period needs to be increased when using a
pull-up resistor to the SDI pin of the following device in the
series. Capacitive loading at the daisy chain node SDO–SDI
between devices must be accounted for to successfully transfer
data. When daisy chaining is used, the
CS
should be kept low
until all the bits of every package are clocked into their respec-
tive serial registers insuring that the address bits and data bits
are in the proper decoding location. This would require 20 bits
of address and data complying to the word format provided in
Table I if two AD8403 four-channel RDACs are daisy chained.
Note, only the AD8403 has a SDO pin. During shutdown
SHDN
the SDO output pin is forced to the off (logic high state)
to disable power dissipation in the pull up resistor. See Figure 40
for equivalent SDO output circuit schematic.
The data setup and data hold times in the specification table de-
termine the data valid time requirements. The last 10 bits of the
data word entered into the serial register are held when
CS
re-
turns high. At the same time
CS
goes high it gates the address
decoder, which enables one of the two (AD8402) or four
(AD8403) positive edge triggered RDAC latches. See Figure 39
detail and Table III Address Decode Table.
Table III. Address Decode Table
A1
A0
Latch Decoded
0
0
1
1
0
1
0
1
RDAC#1
RDAC#2
RDAC#3 AD8403 Only
RDAC#4 AD8403 Only
ADDR
DECODE
RDAC 1
RDAC 4
SERIAL
REGISTER
AD8403
SDI
CLK
CS
Figure 39. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. In the case of the
AD8403 four separate 10-bit data words must be clocked in to
change all four VR settings.
SERIAL
REGISTER
SDI
CK
RS
D
Q
SHDN
CS
CLK
RS
SDO
Figure 40. Detail SDO Output Schematic of the AD8403
All digital pins are protected with a series input resistor and par-
allel Zener ESD structure shown in Figure 41a. This structure
applies to digital pins
CS
, SDI, SDO,
RS
,
SHDN
, CLK. The
digital input ESD protection allows for mixed power supply
applications where +5 V CMOS logic can be used to drive an
AD8400/AD8402 or AD8403 operating from a +3 V power sup-
ply. The analog pins A, B, W are protected with a 20
series
resistor and parallel Zener, see Figure 41b.
1k
DIGITAL
PINS
LOGIC
Figure 41a. Equivalent ESD Protection Circuits
20
A, B, W
Figure 41b. Equivalent ESD Protection Circuit (Analog
Pins)
C
W
120pF
A
B
C
A
C
B
W
C
A
= 90.4pF · ( 256
RDAC
10k
C
B
= 90.4pF · (1 – 256
Figure 42. RDAC Circuit Simulation Model for RDAC =
10 k
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