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參數資料
| 型號： | AD8555ACP-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC16 |
| 封裝： | 4 X 4 MM, MO-220-VGGC, LFCSP-16 |
| 文件頁數： | 27/28頁 |
| 文件大小： | 503K |
| 代理商： | AD8555ACP-R2 |
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AD8555
The bridge circuit with a sensitivity of 2 mV/V is excited by a
5 V supply. The full-scale output voltage from the bridge
(±10 mV) therefore has a common-mode level of 2.5 V. The
AD8555 removes the common-mode component and amplifies
the input signal by a factor of 200 (G1 = 4, G2 = 50, Offset =
128). This results in an output signal of ±2.0 V. In order to pre-
vent this signal from running into the AD8555’s ground rail, the
output offset voltage has to be raised to 2.5 V. This signal is
within the input voltage range of the ADC.
Rev. 0 | Page 27 of 28
USING THE AD8555 WITH CAPACITIVE SENSORS
Figure 61 shows a crude way of using the AD8555 with capaci-
tive sensors. R
P1
and R
P2
are resistors implementing a potential
divider to bias VNEG to VDD/2. Recommended values range
from 1 k to 1 M. C
S
is the capacitive sensor, and R
S
is a shunt
resistor used to prevent leakage currents from integrating on
the sensor. The value of R
S
is application specific.
Note that although VNEG is tied to a dc voltage, the only
impedance across the capacitive sensor is R
S
. Therefore, the only
way for charge to leak away from C
S
is through R
S
, assuming the
input bias currents at VPOS and VNEG are negligible.
R
S
C
S
R
P2
R
P1
AD8555
VOUT
VDD
VPOS
VNEG
0
Figure 61. Crude Way of Using the AD8555 with Capacitive Sensors
The weakness of the circuit in Figure 61 is that the AD8555
input bias current at VPOS flows into R
S
and creates a differen-
tial offset voltage between VPOS and VNEG. This differential
offset voltage is amplified by the AD8555. The input bias cur-
rent at VNEG, on the other hand, flows into R
P1
and create a
common-mode shift. This has little impact on VOUT. Despite
this weakness, the arrangement in Figure 61 should work if the
user wants to minimize the number of components around the
sensor, and if the error introduced by the input bias current at
VPOS is considered negligible.
If greater accuracy is needed, the circuit in Figure 62 is recom-
mended. R
P1
, R
P2
, and C
S
are the same as in Figure 61; R
P1
and
R
P2
should be between 1 k to 1 M. R
S
in Figure 61 has been
split into two resistors, R
S1
and R
S2
, in Figure 62. Again, the only
way for the capacitive sensor to discharge is through (R
S1
+ R
S2
).
The input bias current at VPOS flows through R
S2
and R
P1
, and
the input bias current at VNEG flows through R
S1
and R
P1
. If R
S1
is made equal to R
S2
and if the input bias currents are equal, the
input bias currents give a common-mode shift at VPOS and
VNEG with no differential offset. This common-mode shift is
attenuated by the AD8555 common-mode rejection. Further-
more, changes in input bias current, e.g., with temperature,
manifest as an input common-mode change, also rejected by the
AD8555.
C
S
R
S2
R
P2
R
S1
R
P1
AD8555
VOUT
VDD
VPOS
VNEG
0
Figure 62. Recommended Way of Using the AD8555 with Capacitive Sensors
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| AD8555ACPZ-R2 | 功能描述:IC AMP CHOPPER 2MHZ 10MA 16LFCSP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:DigiTrim® 標準包裝:2,500 系列:Excalibur™ 放大器類型:J-FET 電路數:1 輸出類型:- 轉換速率:45 V/µs 增益帶寬積:10MHz -3db帶寬:- 電流 - 輸入偏壓:20pA 電壓 - 輸入偏移:490µV 電流 - 電源:1.7mA 電流 - 輸出 / 通道:48mA 電壓 - 電源，單路/雙路(±):4.5 V ~ 38 V，±2.25 V ~ 19 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| AD8555ACPZ-R21 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Zero-Drift, Digitally Programmable Sensor Signal Amplifier |
| AD8555ACPZ-REEL | 功能描述:IC AMP CHOPPER 2MHZ 10MA 16LFCSP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:DigiTrim® 標準包裝:50 系列:- 放大器類型:J-FET 電路數:2 輸出類型:- 轉換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 |
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