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參數資料
| 型號： | AD8582AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete Dual 12-Bit DAC |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 2/8頁 |
| 文件大小： | 309K |
| 代理商： | AD8582AR |
AD8582–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
REV. 0
–2–
(@ V
DD
= +5.0 V
±
5%, R
L
= No Load, –40
°
C
≤
T
A
≤
+85
°
C, unless otherwse noted)
Parameter
Symbol
C ondition
Min
T yp
Max
Units
ST AT IC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Full-Scale T empco
N
INL
DNL
V
ZSE
V
T CV
FS
Note 1
12
–2
–1
Bits
LSB
LSB
mV
V
ppm/
°
C
±
3/4
±
3/4
+0.2
4.095
±
16
+2
+1
+3
4.111
Monotonic
Data = 000
H
Data = FFF
,
2
Notes 2 and 3
4.079
MAT CHING PERFORMANCE
Linearity Matching Error
V
FS
A/B
±
1
LSB
REFERENCE OUT PUT
Output Voltage
Output Source Current
Line Rejection
Load Regulation
V
REF
I
LN
REJ
LD
REG
2.484
2.500
2.516
–5
0.08
0.1
V
mA
%/V
%/mA
Note 4
I
REF
= 0 mA to 5 mA
ANALOG OUT PUT
Output Current
Load Regulation at Half Scale
Capacitive Load
I
LD
REG
C
L
Data = 800
R
= 402
to
∞
, Data = 800
H
No Oscillation
3
±
5
3
mA
LSB
pF
1
500
DYNAMIC CHARACT ERIST ICS
3
Crosstalk
Voltage Output Settling T ime
5
Digital Feedthrough
C
T
t
S
F
T
>64
16
35
dB
μ
s
nV s
T o
±
1 LSB of Final Value
Signal Measured at DAC Output, While
Changing Data (
LDA
=
LDB
= “1”)
LOGIC INPUT S
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
V
IL
V
IH
I
IL
C
IL
0.8
V
V
μ
A
pF
2.4
10
10
Note 3
T IMING SPECIFICAT IONS
3, 6
Chip Select Pulse Width
DAC Select Setup
DAC Select Hold
Data Setup
Data Hold
Load Setup
Load Hold
Load Pulse Width
Reset Pulse Width
t
CSW
t
AS
t
AH
t
DS
t
DH
t
LS
t
LH
t
LDW
t
RSW
30
30
0
30
10
20
10
20
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUPPLY CHARACT ERIST ICS
Positive Supply Current
I
DD
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
= +5 V
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
DD
= +5 V
V
DD
=
±
5%
4
1
20
5
0.002
7
2
35
10
0.004
mA
mA
mW
mW
%/%
Power Dissipation
7
P
DISS
Power Supply Sensitivity
PSS
NOT ES
1
1 LSB = 1 mV for 0 V to +4.095 V output range.
2
Includes internal voltage reference error.
3
T hese parameters are guaranteed by design and not subject to production testing.
4
Very little sink current is available at the V
pin. Use external buffer if setting up a virtual ground.
5
Settling time is not guaranteed for the first six codes 0 through 5.
6
All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7
Power dissipation is a calculated value I
DD
×
5 V.
Specifications subject to change without notice.
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