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參數(shù)資料
| 型號： | AD8582AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete Dual 12-Bit DAC |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 309K |
| 代理商： | AD8582AR |
–5–
REV. 0
AD8582
Figures 5 and 6 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full-scale as a function of load. In addition to resis-
tive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
RE FE RE NCE SE CT ION
T he internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. T he voltage generated by the reference is
available at the V
REF
pin. Since V
REF
is not intended to drive ex-
ternal loads, it must be buffered. T he equivalent emitter fol-
lower output circuit of the V
REF
pin is shown in Figure 3.
Bypassing the V
REF
pin will improve noise performance; how-
ever, bypassing is not required for proper operation. Figure 8
shows broadband noise performance.
POWE R SUPPLY
T he very low power consumption of the AD8582 is a direct re-
sult of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8582 is
strongly dependent on the actual logic-input voltage levels
present on the DB0–DB11,
CS
,
A
/B, MSB,
LDA
,
LDB
and
RST
pins. Since these inputs are standard CMOS logic struc-
tures they contribute static power dissipation dependent on the
actual driving logic V
OH
and V
OL
voltage levels. T he graph in
Figure 9 shows the effect on total AD8582 supply current as a
function of the actual value of input logic voltage. Conse-
quently, for optimum dissipation use of CMOS logic versus
T T L provides minimal dissipation in the static state. A V
INL
=
0 V on the DB0–11 pins provides the lowest standby dissipation
of 1 mA typical with a +5 V power supply.
As with any analog system, it is recommended that the AD8582
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection versus fre-
quency performance. T his should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8582 is the wide range of usable supply voltage. T he part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current
capability near full scale can be tolerated, operation of the
AD8582 is possible down to +4.3 volts. T he minimum operat-
ing supply voltage versus load current plot, in Figure 1, pro-
vides information for operation below V
DD
= +4.75 V.
T IMING AND CONT ROL
T he input registers are level triggered and acquire data from the
data bus during the time period when
CS
is low. T he input reg-
ister selected is determined by the
A
/B select pin, see T able I.
for a complete description. When
CS
goes high, the data is
latched into the register and held until
CS
returns low. T he
minimum time required for the data to be present on the bus
before
CS
returns high is called the data setup time (t
DS
) as seen
in T iming Diagram. T he data hold time (t
DH
) is the amount
of time that the data has to remain on the bus after
CS
goes
high. T he high speed timing offered by the AD8582 provides
for direct interface with no wait states in all but the fastest
microprocessors.
T he data from the input registers is transferred to the DAC reg-
isters by the active low
LDA
and
LDB
pins. If these inputs are
tied together, a single logic input can perform a double buffer
update of the DAC registers, which in turn simultaneously
changes the analog output voltages to a new value. If the
LDA
and
LDB
pins are wired low, they become transparent. In this
mode the input register data will directly control the output
voltages. Refer to the Control Logic T ruth
T able for a com-
plete description.
Unipolar Output Operation
T his is the basic mode of operation for the AD8582. T he
AD8582 has been designed to drive loads as low as 820
in par-
allel with 500 pF. T he code table for this operation is shown in
T able II.
T able II. Unipolar Code T able
Hexadecimal
Number in DAC
Register
Decimal Number
in DAC Register
Analog Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+ 4.095
+ 2.049
+ 2.048
+ 2.047
0
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