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參數資料
| 型號： | AD8582CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete Dual 12-Bit DAC |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, UUC24 |
| 封裝： | DIE |
| 文件頁數： | 4/8頁 |
| 文件大小： | 309K |
| 代理商： | AD8582CHIPS |
REV. 0
–4–
AD8582
T able I. Control Logic T ruth T able
CS
A
/B
LDA
LDB
RST
MSB
Input Register
DAC Register
L
L
L
L
H
H
X
X
H
L
H
L
H
X
X
X
X
X
H
H
L
H
L
^
X
X
X
H
H
H
L
L
^
X
X
X
H
H
H
H
H
H
L
L
^
X
X
X
X
X
X
L
H
X
Write to A
Write to B
Write to A
Write to B
Latched
Latched
Reset to Zero Scale
Reset to Midscale
Latch Reset Value
Latched
Latched
A T ransparent
B T ransparent
A & B T ransparent
Latched
Reset to Zero Scale
Reset to Midscale
Latch Reset Value
^Denotes positive edge triggered.
OPE RAT ION
T he AD8582 is a complete, ready-to-use dual 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, laser-
trimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. T he parallel data interface consists of twelve
data bits, DB0–DB11, an address select pin
A
/B, two load
strobe pins (
LDA
,
LDB
) and an active low
CS
strobe. In addi-
tion an asynchronous
RST
pin will set all DAC register bits to
zero causing the V
OUT
to become zero volts, or to midscale for
trimming applications when the MSB pin is programmed to
Logic 1. T his function is useful for power on reset or system
failure recovery to a known state.
D/A CONVE RT E R SE CT ION
T he internal DAC is a 12-bit voltage-mode device with an
output that swings from AGND potential to the 2.5 volt in-
ternal bandgap voltage. It uses a laser trimmed R-2R
ladder which isswitched by N channel MOSFET s. T he out-
put voltageof theDAC has a constant resistance independent
of digital input code. T he DAC output (not available to the
user) isinternally connected to the rail-to-rail output op amp.
AMPLIFIE R SE CT ION
T he internal DAC’s output is buffered by a low power con-
sumption precision amplifier. T his low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zero-
scale DAC output voltages. T he rail-to-rail amplifier is config-
ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
T he op amp has a 16
μ
s typical settling time to 0.01%. T here
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the T ypical Per-
formances section of this data sheet.
Figure 3. Equivalent Schematic of Analog Portion
R1
R2
V
OUT
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
R
BANDGAP
REFERENCE
V
2.5V
2R
R
2R
2R
SPDT
N CH FET
SWITCHES
2R
AV = 4.095/2.5
= 1.638V/V
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
BUFFER
2R
OUT PUT SE CT ION
T he rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 4 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FET s that
will pull an output load directly to GND. T he output sourcing
current is provided by a P channel pull-up device that can sup-
ply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
Figure 4. Equivalent Analog Output Circuit
V
DD
V
OUT
AGND
N-CH
P-CH
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