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參數(shù)資料
| 型號： | AD8600CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Channel, 8-Bit Multiplying DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 2 us SETTLING TIME, 8-BIT DAC, UUC43 |
| 封裝： | DIE |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 236K |
| 代理商： | AD8600CHIPS |
AD8600–SPECIFICATIONS
SINGLE SUPPLY
Parameter
Symbol
Condition
Min
T yp
Max
Units
ST AT IC PERFORMANCE
1
Resolution
Relative Accuracy
2
Differential Nonlinearity
2
Full-Scale Voltage
Full-Scale T empco
Zero Scale Error
N
INL
DNL
V
FS
T CV
FS
V
ZSE
V
ZSE
R
REF
8
–1
–1
2.480
Bits
LSB
LSB
V
ppm/
°
C
LSB
LSB
k
±
1/2
±
1/4
2.490
±
20
+1
+1
2.500
Guaranteed Monotonic
Data = FF
H
Data = FF
H
Data = 00
H
,
RS
= “0,” T
A
= +25
°
C
Data = 00
H
,
RS
= “0”
Data = AB
H
+3.5
+5
Reference Input Resistance
1.2
2
ANALOG OUT PUT
Output Voltage Range
2
Output Current
Capacitive Load
OVR
SS
I
OUT
C
L
V
REF
= +2.5 V
Data = 80
H
No Oscillation
0.000
2.500
V
mA
pF
±
2
50
LOGIC INPUT S
Logic Input Low Voltage
Logic Input High Voltage
Logic Input Current
Logic Input Capacitance
3
V
IL
V
IH
I
IL
C
IL
0.8
V
V
μ
A
pF
2.4
10
10
LOGIC OUT PUT S
Logic Out High Voltage
Logic Out Low Voltage
V
OH
V
OL
I
OH
= –0.4 mA
I
OL
= 1.6 mA
3.5
V
V
0.4
AC CHARACT ERIST ICS
3
Slew Rate
Voltage Output Settling T ime
2
Voltage Output Settling T ime
2
SR
t
S1
t
S2
For
V
REF
or FS Code Change
±
1 LSB of Final Value, Full-Scale Data Change
±
1 LSB of Final Value,
V
REF
= 1 V, Data = FF
H
4
7
2
2
V/
μ
s
μ
s
μ
s
POWER SUPPLIES
Positive Supply Current
Logic Supply Currents
Power Dissipation
Power Supply Sensitivity
Logic Power Supply Range
Positive Power Supply Range
3
I
CC
I
DD1&2
P
DISS
PSS
V
DDR
V
CCR
V
IH
= 5 V, V
IL
= 0 V, No Load
V
IH
= 5 V, V
IL
= 0 V, No Load
V
IH
= 5 V, V
IL
= 0 V, No Load
V
CC
=
±
5%
24
35
0.1
175
0.007
5.25
7.0
mA
mA
mW
%/%
V
V
120
4.75
V
DD
NOT ES
1
When V
REF
= 2.500 V, 1 LSB = 9.76 mV.
2
Single supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (V
EE
) pin of at least –0.7 V to
–5.25 V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 7
10
to 80
10
.
3
Guaranteed by design not subject to production test.
Specifications subject to change without notice.
REV. 0
–2–
(@V
DD1
= V
DD2
= V
CC
= +5V
±
5%, V
EE
= 0V, V
REF
= +2.500V, –40
°
C
≤
T
A
≤
+85
°
C, unless otherwse noted)
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