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參數資料
| 型號： | AD8600CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Channel, 8-Bit Multiplying DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 2 us SETTLING TIME, 8-BIT DAC, UUC43 |
| 封裝： | DIE |
| 文件頁數： | 8/16頁 |
| 文件大小： | 236K |
| 代理商： | AD8600CHIPS |
REV. 0
–8–
AD8600
*Patent Pending.
Figure 14. Supply Current vs. Temperature
Figure 15. Output Voltage Drift
Accelerated by Burn-In
S
TEMPERATURE –
°
C
20
15
16
18
17
19
125
–50
–75
100
25
50
–25
0
75
V
CC
= +5V
V
EE
= –5V
V
REF
= 3.5V
χ
χ + 3σ
χ 3σ
T = HOURS OF OPERATION AT +125
°
C
C
1200
200
0
1000
600
800
400
χ
χ + 3σ
χ 3σ
V
CC
= +5V
V
EE
= –5V
V
= 3.5V
CODE = 00
H
–2
–4
0
2
4
1
3
5
–1
–3
–5
Operation
T he AD8600 is a 16-channel voltage output, 8-bit digital to
analog converter. T he AD8600 operates from a single +5 V
supply, or for a wider output swing range, the part can operate
from dual supplies of
±
5 V or
±
6 V or a single supply of +7 V.
T he DACs are based upon a unique R-2R ladder structure*
that removes the possibility of current injection from the refer-
ence to ground during code switching. Each of the 8-bit DACs
has an output amplifier to provide 16 low impedance outputs.
With a single external reference, 16 independent dc output lev-
els can be programmed through a parallel digital interface. T he
interface includes 4 bits of address (A0–A3), 8 bits of data
(DB0–DB7), a read/write select pin (R/
W
), an enable clock
strobe (
EN
), a DAC register load strobe (
LD
), and a chip select
pin (
CS
). Additionally a reset pin (
RS
) is provided to asynchro-
nously reset all 16 DACs to 0 V output.
D/A Converter Section
T he internal DAC is an 8-bit voltage mode devicewith an out-
put that swings from DACGND to the external reference volt-
age, V
REF
. T he equivalent schematic of one of the DACs is
shown in Figure 16. T he DAC uses an R-2R ladder to ensure
accuracy and linearity over the full temperature range of the part.
T he switches shown are actually N and P-channel MOSFET s to
allow maximum flexibility and range in the choice of reference
R
R
R
V
OUT
R
R
R
2R
R
R
R
R
R
TO 15
DACs
V
REF
DACGND
*R = 30k
TYPICALLY
Figure 16. Equivalent Schematic of Analog Channel
voltage. T he switches’ low ON resistance and matching is im-
portant in maintaining the accuracy of the R-2R ladder.
Amplifier Section
T he output of the DAC ladder is buffered by a rail-to-rail out-
put amplifier. T his amplifier is configured as a unity gain fol-
lower as shown in Figure 16. T he input stage of the amplifier
contains a PNP differential pair to provide low offset drift and
noise. T he output stage is shown in Figure 17. It employs
complementary bipolar transistors with their collectors con-
nected to the output to provide rail-to-rail operation. T he NPN
transistor enters into saturation as the output approaches the
negative rail. T hus, in single supply, the output low voltage is
limited by the saturation voltage of the transistor. For the tran-
sistors used in the AD8600, this is approximately 40 mV. T he
AD8600 was not designed to swing to the positive rail in con-
trast to some of ADI’s other DACs (for example, the AD8582).
T he output stage of the amplifier is actually capable of swinging
to the positive rail, but the input stage limits this swing to ap-
proximately 1.0 V below V
CC
.
V
EE
V
OUT
V
CC
Figure 17. Equivalent Analog Output Circuit
During normal operation, the output stage can typically source
and sink
±
1 mA of current. However, the actual short circuit
current is much higher. In fact, each DAC is capable of sourc-
ing 20 mA and sinking 8 mA during a short condition. T he
absolute maximum ratings state that, at most, four DACs can
be shorted simultaneously. T his restriction is due to current
densities in the metal traces. If the current density is too high,
voltage drops in the traces will cause a loss in linearity perfor-
mance for the other DACs in the package. T hus to ensure long-
term reliability, no more than four DACs should be shorted
simultaneously.
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