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參數資料
| 型號： | AD9101SE |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 125 MSPS Monolithic Sampling Amplifier |
| 中文描述： | TRACK AND HOLD AMPLIFIER, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數： | 2/12頁 |
| 文件大小： | 247K |
| 代理商： | AD9101SE |
REV. 0
–2–
AD9101–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(+V
S
= +5 V, –V
S
= –5.2 V, R
LOAD
= 100
V
, R
lN
= 50
V
unless otherwse noted)
T est
Level
AD9101
T yp
Parameter
Conditions
T emp
Min
Max
Units
DC ACCURACY
Gain
V
IN
= 0.5 V
V
IN
= 0.5 V
V
IN
= 0 V
V
IN
= 0 V
25
°
C
Full
25
°
C
Full
25
°
C
Full
25
°
C
Full
Full
I
VI
I
VI
V
VI
VI
V
V
3.93
3.9
4
4.07
4.1
±
10
±
15
V/V
V/V
mV
mV
mA
dB
mV/V
mV/V
Offset
±
3
Output Resistance
Output Drive Capability
PSRR
Pedestal Sensitivity to Positive Supply
Pedestal Sensitivity to Negative Supply
ANALOG INPUT /OUT PUT
Output Voltage Range
Input Bias Current
0.4
±
70
43
4
8
±
60
37
V
S
= 0.5 V p-p
V
S
= 0.5 V p-p
V
S
= 0.5 V p-p
Full
25
°
C
Full
25
°
C
25
°
C–T
MAX
T
MIN
VI
I
VI
V
VI
VI
±
2.4
±
2.7
±
5
V
μ
A
μ
A
pF
k
k
±
15
±
20
Input Capacitance
Input Resistance
2
125
30
25
CLOCK /
CLOCK
INPUT S
Input Bias Current
Input Low Voltage (V
IL
)
1
Input High Voltage (V
IH
)
1
T RACK MODE DYNAMICS
Bandwidth (–3 dB)
Slew Rate
Overdrive Recovery T ime
2
(to 0.1%)
Integrated Output Noise
Input RMS Spectral Noise @ 10 MHz
HOLD MODE DYNAMICS
Worst Harmonic (23 MHz, 50 MSPS)
Worst Harmonic (48 MHz, 100 MSPS)
Worst Harmonic (48 MHz, 100 MSPS)
Worst Harmonic (48 MHz, 100 MSPS)
Worst Harmonic (48 MHz, 125 MSPS)
Sampling Bandwidth (–3 dB)
3
Hold Noise
4
(RMS)
Droop Rate
CL/
CL
= –1.0 V
V
IN
= 0.5 V p-p
V
IN
= 0.5 V p-p
Full
Full
Full
VI
VI
VI
3
3.6
–1.5
–0.8
mA
V
V
–1.8
–1.0
V
OUT
= 1 V p-p
4 Volt Output Step
V
IN
=
±
1 V to 0 V
(5 MHz–200 MHz) 25
°
C
Full
Full
25
°
C
IV
IV
V
V
V
160
1300
250
1800
55
210
3.3
MHz
V/
μ
s
ns
μ
V
μ
V/
√
Hz
25
°
C
V
OUT
= 2 V p-p
V
OUT
= 2 V p-p
V
OUT
= 2 V p-p
V
OUT
= 2 V p-p
V
OUT
= 2 V p-p
V
IN
= 0.5 V p-p
25
°
C
25
°
C
Full (Ind.)
Full (Mil.)
25
°
C
25
°
C
Full
25
°
C
Full
Full
V
IV
IV
IV
V
V
V
I
VI
V
–75
–62
dBFS
dBFS
dBFS
dBFS
dBFS
MHz
mV/s
mV/
μ
s
mV/
μ
s
dB
–57
–53
–51
–57
350
150
×
t
H
±
5
±
18
±
40
Feedthrough Rejection (50 MHz)
T RACK -T O-HOLD SWIT CHING
Aperture Delay
Aperture Jitter
Pedestal Offset
V
OUT
= 2 V p-p
–66
25
°
C
25
°
C
25
°
C
Full
Full
Full
25
°
C
V
V
I
VI
V
V
V
–250
<1
±
5
ps
ps rms
mV
mV
mV
ns
pV-s
V
IN
= 0 V
V
IN
= 0 V
V
IN
= 0 V
V
IN
= 0 V
V
IN
= 0 V
±
20
±
35
T ransient Amplitude
Settling T ime to 4 mV
Glitch Product
5
HOLD-T O-T RACK SWIT CHING
Acquisition T ime to 0.1%
Acquisition T ime to 0.01%
8
4
20
2 V Output Step
2 V Output Step
2 V Output Step
25
°
C
25
°
C
Full
V
IV
IV
7
11
ns
ns
ns
14
16
POWER SUPPLY
+V
S
Current
–V
S
Current
Power Dissipation
Full
Full
Full
VI
VI
VI
55
59
570
70
73
715
mA
mA
mW
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