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參數資料
| 型號： | AD9200JRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SSOP-28 |
| 文件頁數： | 8/24頁 |
| 文件大小： | 338K |
| 代理商： | AD9200JRS |
AD9200
–8–
REV. E
Table I. Mode Selection
Input
Connect
Input
Span
MODE
Pin
REFSENSE
Pin
Modes
REF
REFTS
REFBS
Figure
TOP/BOTTOM
AIN
1 V
AVDD
Short REFSENSE, REFTS and VREF Together
AGND
18
AIN
2 V
AVDD
AGND
Short REFTS and VREF Together
AGND
19
CENTER SPAN
AIN
1 V
AVDD/2
Short VREF and REFSENSE Together
AVDD/2
AVDD/2
20
AIN
2 V
AVDD/2
AGND
No Connect
AVDD/2
AVDD/2
Differential
AIN Is Input 1
1 V
AVDD/2
Short VREF and REFSENSE Together
AVDD/2
AVDD/2
29
REFTS and
REFBS Are
Shorted Together
for Input 2
2 V
AVDD/2
AGND
No Connect
AVDD/2
AVDD/2
External Ref
AIN
2 V max
AVDD
AVDD
No Connect
Span = REFTS
– REFBS (2 V max)
Short to
VREFTF
21, 22
AGND
Short to
VREFBF
23
AD876
AIN
2 V
Float or
AVSS
AVDD
No Connect
Short to
VREFTF
Short to
VREFBF
30
0
–9
1.0E+6
1.0E+9
10.0E+6
S
100.0E+6
–3
–6
FREQUENCY – Hz
–12
–15
–18
–21
–24
–27
Figure 13. Full Power Bandwidth
25
20
–25
0
3.0
1.0
2.0
15
10
–5
–10
–15
INPUT VOLTAGE – V
5
0
–20
2.5
0.5
1.5
I
B
m
A
REFBS = 0.5V
REFTS = 2.5V
CLOCK = 20MHz
Figure 14. Input Bias Current vs. Input Voltage
APPLYING THE AD9200
THEORY OF OPERATION
The AD9200 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9200 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9200 requires a small fraction of the
1023 comparators used in a traditional flash type A/D. A
sample-and-hold function within each of the stages permits the
first stage to operate on a new input sample while the second,
third and fourth stages operate on the three preceding samples.
OPERATIONAL MODES
The AD9200 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876 A/D.
To realize this flexibility, internal switches on the AD9200 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as the Table I should
assist in picking the desired mode.
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| AD9200JRSRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 20Msps 10-bit Parallel 28-Pin SSOP T/R |
| AD9200JRSZ | 功能描述:IC ADC 10BIT CMOS 20MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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