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參數資料
| 型號： | AD9203 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter |
| 中文描述： | 10位，40 MSPS的，3伏，74毫瓦的A / D轉換器 |
| 文件頁數： | 11/19頁 |
| 文件大小： | 216K |
| 代理商： | AD9203 |
REV. 0
AD9203
–11–
Figure 19 shows the reference programmed by external resistors
for 0.75 V. This will set the ADC to receive a 1.5 V span cen-
tered about 0.75 V. The reference is programmed according to
the algorithm
VREF
= 0.5
V
×
[1 + (
RA/RB
)]
ADC
CORE
+
–
LOGIC
0.1
m
F
10
m
F
AINP
AINN
VREF
0.5V
REFTF
REFBF
1.125V
REFSENSE
1.5V
0V
R
A
R
B
0.1
m
F
1.875V
0.1
m
F
0.1
m
F
10
m
F
AD9203
Figure 19. Programmable Reference Configuration
EXTERNAL REFERENCE OPERATION
Figure 20 illustrates the use of an external reference. An exter-
nal reference may be necessary for several reasons. Tighter
reference tolerance will enhance the accuracy of the ADC and
will allow lower temperature drift performance. When several
ADC’s track one another, a single reference (internal or exter-
nal) will be necessary. The AD9203 will draw less power when
an external reference is used.
When the REFSENSE pin is tied to AVDD, the internal refer-
ence will be disabled, allowing the use of an external reference.
The AD9203 contains an internal reference buffer. It will load
the external reference with an equivalent 10 k
load. The inter-
nal buffer will generate positive and negative full-scale references
for the ADC core.
In Figure 20, an external reference is used to set the midscale
set point for single-ended use. At the same time, it sets the input
voltage span through a resistor divider. If the ADC is being
driven differentially through a transformer, the external refer-
ence can set the center tap (common-mode voltage).
1.0V
2.0V
0.1
m
F
10
m
F
VREF
AD9203
+5V
0.1
m
F
1.5k
V
0.1
m
F
3.0V
REFSENSE
A3
AVDD
AINP
AINN
EXTERNAL
REF (2V)
1V
1.5k
V
Figure 20. External Reference Configuration
CLAMP OPERATION
The AD9203 contains an internal clamp. It may be used when
operating the input in a single-ended mode. The AD9203’s
clamp is very useful for clamping NTSC and PAL video signals
to ground. The clamp cannot be used in the differential input
mode.
1V p-p
0Vdc
ADC
CORE
REFSENSE
VREF
AINN
CIN
CLAMP
IN
CLAMP
AD9203
AINP
SW1
50
V
TYP
Figure 21. Clamp Configuration (VREF = 0.5 V)
Figure 21 shows the internal clamp circuitry and the external
control signals needed for clamp operation. To enable the clamp,
apply a logic high “1” to the CLAMP pin. This will close the
internal switch SW1. SW1 is opened by asserting the CLAMP
pin low “0.” The capacitor holds the voltage across C
IN
con-
stant until the next interval. The charge on the capacitor will
leak off as a function of input bias current (see Figure 22).
INPUT VOLTAGE – Volts
250
200
0
3
0.5
I
m
A150
100
50
0
–50
1
1.5
2
2.5
Figure 22. Input Bias Current vs. Input Voltage
(F
S
= 40 MSPS)
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