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參數資料
| 型號： | AD9214-105PCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 65/80/105 MSPS 3 V A/D Converter |
| 中文描述： | 10位，65/80/105MSPS的3V A/D轉換器 |
| 文件頁數： | 7/20頁 |
| 文件大小： | 447K |
| 代理商： | AD9214-105PCB |
REV. D
AD9214
–7–
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differen-
tial voltage is computed by observing the voltage on a single
pin and subtracting the voltage from the other pin, which is
180 degrees out of phase. Peak-to-peak differential is computed
by rotating the inputs phase 180 degrees and taking the peak
measurement again. Then the difference is computed between
both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
ENOB
SINAD
dB
FullScale
Actual
MEASURED
=
+
–
.
1 76
log
.
20
6 02
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic
“
1
”
state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be left
in low state. See timing implications of changing t
ENCH
in text. At a
given clock rate, these specs define an acceptable Encode duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Power
V
Z
0 001
.
FULL SCALE
FULL SCALE rms
INPUT
=
10
2
log
Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a
“
best straight line
”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Noise (for any range within the ADC)
V
Z
FS
SNR
Signal
NOISE
dBm
dBc
10
dBFS
=
×
0 001 10
.
Where
Z
is the input impedance,
FS
is the full-scale of the
device for the frequency in question,
SNR
is the value for the
particular input level and Signal is the signal level within the
ADC reported in dB below full-scale. This value includes both
thermal and quantization noise.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an intermodulation distortion product. May
be reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
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相關代理商/技術參數 |
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|---|---|
| AD9214-65PCB | 制造商:Analog Devices 功能描述:10 BIT 65 MSPS A/D CONVERTER EVAL BOARD - Bulk |
| AD9214BRS-105 | 功能描述:IC ADC 10BIT 105MSPS 3V 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9214BRS-65 | 功能描述:IC ADC 10BIT 65MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9214BRS-80 | 功能描述:IC ADC 10BIT 80MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9214BRSRL105 | 制造商:AD 功能描述:New |
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