- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373960 > AD9215BCP-105 (ANALOG DEVICES INC) 10-Bit, 65/80/105 MSPS, 3V A/D Converter PDF資料下載
參數(shù)資料
| 型號： | AD9215BCP-105 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 1416K |
| 代理商： | AD9215BCP-105 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD9215
Table 7. Reference Configuration Summary
Selected Mode
Externally Supplied Reference AVDD
Internal 0.5 V Reference
Programmed Variable
Reference
Internally Programmed 1 V
Reference
Table 8. Digital Output Coding
Code VIN+ VIN Input Span =
2 V p-p (V)
1023
1.000
512
0
511
0.00195
0
1.00
Rev. A | Page 16 of 36
External SENSE
Connection
Internal Op Amp
Configuration
N/A
Voltage Follower (G = 1)
Noninverting (1 < G < 2)
Resulting VREF
(V)
N/A
0.5
0.5 × (1 +
R2
/
R1
)
Resulting Differential Span
(V p-p)
2 × External Reference
1.0
2 × VREF
VREF
External Divider
AGND to 0.2 V
Internal Divider
1.0
2.0
VIN+ VIN Input Span =
1 V p-p (V)
0.500
0
0.000978
0.5000
Digital Output Offset Binary
(D9D0)
11 1111 1111
10 0000 0000
01 1111 1111
00 0000 0000
Digital Output Twos
Complement (D9D0)
01 1111 1111
00 0000 0000
11 1111 1111
10 0000 0000
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
INPUT
) due only to aperture jitter (t
A
) can be
calculated with the following equation
SNR Degradation
=
20 × log
10
[2 × π
×
f
INPUT
×
t
A
]
In the equation, the rms aperture jitter,
t
A
, represents the root-
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9215. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
Power Dissipation and Standby Mode
As shown in Figure 35, the power dissipated by the AD9215 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
I
DRVDD
=
V
DRVDD
×
C
LOAD
×
f
CLOCK
×
N
where
N
is the number of output bits, 10 in the case of the
AD9215. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full-scale square wave at the Nyquist frequency,
f
CLOCK
/2. In
practice, the DRVDD current is established by the average num-
ber of output bits switching, which are determined by the encode
rate and the characteristics of the analog input signal.
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 35 was taken with a 5 pF load on each output driver.
0
15
35
30
25
20
40
105
5
15
25
35
45
f
SAMPLE
(MSPS)
55
65
75
85
95
I
A
I
D
–1
1
3
5
7
9
11
13
15
AD9215-105 I
AVDD
AD9215-65/80 I
AVDD
I
DRVDD
Figure 35. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9215 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9215 into its normal opera-
tional mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9215BCP-105EB | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215BCP-65 | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215BCP-65EB | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215 | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215BCP-80 | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9215BCP-105EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9215 3 V A/D Converter ,10-Bit, 65/80/105 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9215 3V A/D CNVRTR ,10-BIT, 65/80/105 MSPS - Bulk |
| AD9215BCP-105EBZ | 功能描述:BOARD EVAL FOR AD9215BCP-105 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9215BCP-65 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 65Msps 10-bit Parallel 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT LOW POWER 65/80/105 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:10BIT ADC 65MSPS 9215 LFCSP-32 |
| AD9215BCP-65EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9215 3V A/D CNVRTR ,10-BIT, 65/80/105 MSPS - Bulk |
| AD9215BCP-65EBZ | 功能描述:BOARD EVAL FOR AD9215BCP-65 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。