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參數資料
型號: AD9220ARS
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
中文描述: 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: MO-150AH, SSOP-28
文件頁數: 5/28頁
文件大小: 350K
代理商: AD9220ARS
AD9221/AD9223/AD9220
REV. D
–5–
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
GAIN ERROR
The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full
scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal differ-
ence between first and last code transitions.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25
°
C) value to the value at
T
MIN
or T
MAX
.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N
= (
SINAD
– 1.76)/6.02
it is possible to get a measure of performance expressed as
N
,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
PIN CONNECTIONS
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9221/
AD9223/
AD9220
CLK
AVSS
AVDD
DVSS
DVDD
(LSB) BIT 12
BIT 11
BIT 10
CML
VINA
VINB
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
REFCOM
CAPB
CAPT
BIT 3
BIT 2
(MSB) BIT 1
OTR
VREF
AVDD
AVSS
SENSE
PIN FUNCTION DESCRIPTIONS
Pin
Number Name
Description
1
2
3–12
13
14
15, 26
16, 25
17
18
19
20
21
22
23
24
27
28
CLK
BIT 12
BIT N
BIT 1
OTR
AVDD
AVSS
SENSE
VREF
REFCOM
CAPB
CAPT
CML
VINA
VINB
DVSS
DVDD
Clock Input Pin
Least Significant Data Bit (LSB)
Data Output Bit
Most Significant Data Bit (MSB)
Out of Range
+5 V Analog Supply
Analog Ground
Reference Select
Reference I/O
Reference Common
Noise Reduction Pin
Noise Reduction Pin
Common-Mode Level (Midsupply)
Analog Input Pin (+)
Analog Input Pin (–)
Digital Ground
+3 V to +5 V Digital Supply
DEFINITIONS OF SPECIFICATION
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
相關PDF資料
PDF描述
AD9221 Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9221AR RES, 18.2K, 1/4, 1%, MF
AD9221ARS Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9223 Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9223AR Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
相關代理商/技術參數
參數描述
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AD9220ARSZ 制造商:Analog Devices 功能描述:IC ADC 12BIT 10MSPS ((NW)) 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 10MSPS, SSOP-28
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