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| 型號： | AD9230BCPZ11-200 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 11-BIT 200MSPS 56-LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 373mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 配用： | AD923011-200EBZ-ND - BOARD EVAL FOR AD9230 200MSPS |
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11-Bit, 200 MSPS,
1.8 V Analog-to-Digital Converter
AD9230-11
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2008 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 62.5 dBFS @ fIN up to 70 MHz @ 200 MSPS
ENOB of 10.2 @ fIN up to 70 MHz @ 200 MSPS (1.0 dBFS)
SFDR = 77 dBc @ fIN up to 70 MHz @ 200 MSPS (1.0 dBFS)
Excellent linearity
DNL = ±0.15 LSB typical
INL = ±0.5 LSB typical
LVDS at 200 MSPS (ANSI-644 levels)
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold amplifier
Low power dissipation
373 mW @ 200 MSPS (LVDS SDR mode)
328 mW @ 200 MSPS (LVDS DDR mode)
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
AGND
PWDN
RBIAS
AVDD
VIN+
VIN–
CML
TRACK-AND-HOLD
REFERENCE
ADC
12-BIT
CORE
OUTPUT
STAGING
LVDS
CLK+
CLK–
CLOCK
MANAGEMENT
SERIAL PORT
RESET SCLK SDIO
CSB
DCO–
DCO+
OR–
OR+
D10 TO D0
DRGND
DRVDD
12
11
AD9230-11
07
10
1-
0
01
Figure 1.
GENERAL DESCRIPTION
The AD9230-11 is an 11-bit monolithic sampling analog-to-
digital converter (ADC) optimized for high performance,
low power, and ease of use. The product operates at up to a
200 MSPS conversion rate and is optimized for outstanding
dynamic performance in wideband carrier and broadband
systems. All necessary functions, including a track-and-hold
(T/H) amplifier and voltage reference, are included on the
chip to provide a complete signal conversion solution.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support twos
complement, offset binary format, or Gray code. A data clock
output is available for proper output data timing.
Fabricated on an advanced CMOS process, the AD9230-11 is
available in a 56-lead lead frame chip scale package, specified
over the industrial temperature range (40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
High Performance. Maintains 62.5 dBFS SNR
@ 200 MSPS with a 70 MHz input.
2.
Low Power. Consumes only 373 mW @ 200 MSPS.
3.
Ease of Use. LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4.
Serial Port Control. Standard serial port interface (SPI)
supports various product functions, such as data formatting,
disabling the clock duty cycle stabilizer, power-down, gain
adjust, and output test pattern generation.
5.
Pin-Compatible Family. 10-bit and 12-bit pin-compatible
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