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參數資料
| 型號： | AD9241 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的14位，125 MSPS的單片機的A / D轉換器 |
| 文件頁數： | 10/24頁 |
| 文件大?。?/td> | 495K |
| 代理商： | AD9241 |
AD9241
REV. 0
–10–
10μF
VINA
VINB
SENSE
AD9241
0.1μF
R
S
*
V
CC
V
EE
R
S
*
VREF
REFCOM
*OPTIONAL SERIES RESISTOR
Figure 25. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several fac-
tors, including the AD9241 sampling rate, the selected op amp
and the particular application. In most applications, a 30
to
50
resistor is sufficient
.
Some applications may require a
larger resistor value to reduce the noise bandwidth or possibly
limit the fault current in an overvoltage condition. Other appli-
cations may require a larger resistor value as part of an antialiasing
filter. In any case, since the THD performance is dependent on
the series resistance and the above mentioned factors, optimiz-
ing this resistor value for a given application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance con-
nected to VINA and VINB. The degree of improvement is depen-
dent on the resistor value and the sampling rate. For series
resistor values greater than 100
, the use of a matching
resistor is encouraged.
The noise or small-signal bandwidth of the AD9241 is the same
as its full-power bandwidth. For noise sensitive applications, the
excessive bandwidth may be detrimental and the addition of a
series resistor and/or shunt capacitor can help limit the wide-
band noise at the A/D’s input by forming a low-pass filter. Note,
however, that the combination of this series resistance with the
equivalent input capacitance of the AD9241 should be evalu-
ated for those time-domain applications that are sensitive to the
input signal’s absolute settling time. In applications where har-
monic distortion is not a primary concern, the series resistance
may be selected in combination with the SHA’s nominal 16 pF
of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9241, a lower series resistance can be selected
to establish the filter’s cutoff frequency while not degrading the
distortion performance of the device. The shunt capacitance
also acts as a charge reservoir, sinking or sourcing the additional
charge required by the hold capacitor, C
H
, further reducing
current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9241 should be evaluated. To optimize performance
when noise is the primary consideration, increase the shunt
capacitance as much as the transient response of the input signal
will allow. Increasing the capacitance too much may adversely
affect the op amp’s settling time, frequency response and distor-
tion performance.
Table I. Analog Input Configuration Summary
Input
Connection
Single-Ended
Input
Span (V)
2
Input Range (V)
VINA
1
0 to 2
Figure
#
32, 33
Coupling
DC
VINB
1
1
Comments
Best for stepped input response applications, suboptimum
THD and noise performance, requires
±
5 V op amp.
2
×
VREF
0 to
2
×
VREF
VREF
32, 33
Same as above but with improved noise performance due to
increase in dynamic range. Headroom/settling time require-
ments of
±
5 V op amp should be evaluated.
5
0 to 5
2.5
32, 33
Optimum noise performance, excellent THD performance. Requires
op amp with VCC > +5 V due to insufficient headroom @ 5 V.
2
×
VREF
2.5 – VREF
to
2.5 + VREF
2.5
39
Optimum THD performance with VREF = 1, noise performance
improves while THD performance degrades as VREF increases
to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.
Single-Ended
AC
2 or
2
×
VREF
0 to 1 or
0 to 2
×
VREF
1 or VREF
34
Suboptimum ac performance due to input common-mode
level not biased at optimum midsupply level (i.e., 2.5 V).
5
2
×
VREF
0 to 5
2.5
34
Optimum noise performance, excellent THD performance.
2.5 – VREF
to
2.5 + VREF
2.5
35
Flexible input range, Optimum THD performance with
VREF = 1. Noise performance improves while THD performance
degrades as VREF increases to 2.5 V.
Differential
AC or
DC
2
2 to 3
3 to 2
29–31
Optimum full-scale THD and SFDR performance well beyond
the A/Ds Nyquist frequency.
2
×
VREF
2.5 – VREF/2
to
2.5 + VREF/2
2.5 + VREF/2
to
2.5 – VREF/2
29–31
Same as 2 V to 3 V input range with the exception that full-scale
THD and SFDR performance can be traded off for better noise
performance.
5
1.25 to 3.75
3.75 to 1.25
29–31
Widest dynamic range (i.e., ENOBs) due to Optimum Noise
performance.
1
VINA and VINB can be interchanged if signal inversion is required.
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相關代理商/技術參數 |
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|---|---|
| AD9241ACHIPS | 制造商:Analog Devices 功能描述: |
| AD9241AS | 制造商:Analog Devices 功能描述:ADC Single Pipelined 1.25Msps 14-bit Parallel 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:14BIT 1.25 MSPS MONOLITHIC A/D CONVERTER - Bulk 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
| AD9241ASRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 1.25Msps 14-bit Parallel 44-Pin MQFP T/R |
| AD9241ASZ | 功能描述:IC ADC 14BIT 1.25MSPS 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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