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參數(shù)資料
| 型號： | AD9245BCP-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80 MSPS, 3 V A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | EXPOSED PAD, MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 1510K |
| 代理商： | AD9245BCP-80 |
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AD9245
TIMING
The AD9245 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (t
PD
) after the rising edge of the clock signal. Refer to
for a detailed timing diagram.
Figure 2
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9245. These transients can degrade the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9245 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9245. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9245 using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are summarized
in the following sections.
and described
Table 8
Table 8
Table 8. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap (com-
mon-mode voltage).
INTERNAL REFERENCE CONNECTION
A comparator within the AD9245 detects the potential at the
SENSE pin and configures the reference into one of four
possible states, which are summarized in
grounded, the reference amplifier switch is connected to the
internal resistor divider (see
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as follows:
. If SENSE is
), setting VREF to 1 V.
Figure 33
, the switch is again set to the
Figure 33. Internal Reference Configuration
Figure 35
1
×
=
R1
R2
VREF
5
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
03583-B-017
10
μ
F+
0.1
μ
F
VREF
SENSE
0.5V
AD9245
VIN–
VIN+
REFT
0.1
μ
F
0.1
μ
F
10
μ
F
0.1
μ
F
REFB
SELECT
LOGIC
ADC
CORE
+
If the internal reference of the AD9245 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 34
depicts how the internal reference voltage is affected by loading.
LOAD (mA)
E
0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
0358
3-B
-019
0
–0.25
–0.20
–0.15
–0.10
–0.05
0.5V ERROR (%)
1.0V ERROR (%)
Figure 34. VREF Accuracy vs. Load
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Internal Switch
Position
N/A
SENSE
SENSE
Resulting VREF (V)
N/A
0.5
+
×
R1
1.0
Resulting Differential
Span (V p-p)
2 × External Reference
1.0
2 × VREF
R2
5
(See Figure 35)
Internal Fixed Reference
AGND to 0.2 V
Internal Divider
2.0
Rev. B | Page 17 of 28
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