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參數(shù)資料
| 型號(hào)： | AD9245BCP-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80 MSPS, 3 V A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | EXPOSED PAD, MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 1510K |
| 代理商： | AD9245BCP-80 |
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AD9245
AD9245–SWITCHING SPECIFICATIONS
Table 4. AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted
Parameter
AD9245BCP
Typ
4.2
7
1
0.3
7
2
Temp
Test Level
Min
80
12.5
4.6
4.6
Max
1
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulsewidth High
1
CLK Pulsewidth Low
1
DATA OUTPUT PARAMETERS
Output Propagation Delay (t
PD
)
2
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter, t
J
)
Wake-Up Time
3
OUT-OF-RANGE RECOVERY TIME
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
V
V
V
V
V
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3
Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
t
A
2.0ns MIN
t
PD
= 6.0ns MAX
03583-B-002
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level
Definitions
I
100% production tested.
II
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. B | Page 6 of 28
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