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參數資料
型號: AD9248BCPZRL7-65
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit, 20/40/65 MSPS Dual A/ D Converter
中文描述: DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC64
封裝: 9 X 9 MM, MO-220VMMD, LFCSP-64
文件頁數: 6/23頁
文件大?。?/td> 419K
代理商: AD9248BCPZRL7-65
AD9248
Preliminary Technical Data
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications
Rev. PrE | Page 6 of 23
Test
AD9248BST/BCP-
20
Min
Typ
20
50.0
15.0
15.0
2
3.5
7
1.0
0.5
2.5
2
AD9248BST/BCP-
40
Min
Typ
40
25.0
8.8
8.8
2
3.5
7
1.0
0.5
2.5
2
AD9248BST/BCP-
65
Min
Typ
65
15.4
6.2
6.2
2
3.5
7
1.0
0.5
2.5
2
Parameter
SWITCHING PERFORMANCE
Max Conversion Rate
Min Conversion Rate
CLK Period
CLK Pulsewidth High
1
CLK Pulsewidth Low
1
DATA OUTPUT PARAMETER
Output Delay
2
(t
PD
)
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (t
J
)
Wake-Up Time
3
OUT-OF-RANGE RECOVERY
TIME
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Level
VI
V
V
V
V
VI
V
V
V
V
V
Max
1
6
Max
1
6
Max
1
6
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
Ps rms
ms
1
The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC 20).
2
Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Specifications subject to change without notice.
相關PDF資料
PDF描述
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