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參數資料
| 型號： | AD9281-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Channel 8-Bit Resolution CMOS ADC |
| 中文描述： | 雙通道8位分辨率的CMOS模數轉換器 |
| 文件頁數： | 5/19頁 |
| 文件大小： | 406K |
| 代理商： | AD9281-EB |
AD9281
–5–
REV. E
DRVDD
AVSS
DRVSS
DRVSS
AVDD
AVDD
AVSS
AVSS
AVDD
REFBS
REFBF
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
IN
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
AVDD
AVSS
d. INA, INB
e. Reference
Figure 2. Equivalent Circuits
f. REFSENSE
g. VREF
OFFSET ERROR
The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-
tion from that point.
OFFSET MATCH
The change in offset error between I and Q channels.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N
= (
SINAD
– 1.76)/6.02
It is possible to get a measure of performance expressed as
N
,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
GAIN ERROR
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
scale. Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal difference
between the first and last code transitions.
GAIN MATCH
The change in gain error between I and Q channels.
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising clock edge.
MUX SELECT DELAY
The delay between the change in SELECT pin data level and
valid data on output pins.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
APERTURE DELAY
Aperture delay is a measure of the Sample-and-Hold Amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
a. D0–D9 b. Three-State Standby c. CLK
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| AD9283BRS-100Z | 制造商:Analog Devices 功能描述:ADC 8BIT 100MSPS 0.75LSB 20SSOP 制造商:Analog Devices 功能描述:ADC, 8BIT, 100MSPS, 0.75LSB, 20SSOP 制造商:Analog Devices 功能描述:ADC, 8BIT, 100MSPS, 0.75LSB, 20SSOP, Resolution (Bits):8bit, Sampling Rate:100MS 制造商:Analog Devices 功能描述:ADC, 8BIT, 100MSPS, 0.75LSB, 20SSOP, Resolution (Bits):8bit, Sampling Rate:100MSPS, Supply Voltage Type:Single, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Digital IC Case Style:SSOP, No. of Pins:20, Input Channel , RoHS Compliant: Yes |
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