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參數資料
| 型號： | AD9281-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Channel 8-Bit Resolution CMOS ADC |
| 中文描述： | 雙通道8位分辨率的CMOS模數轉換器 |
| 文件頁數： | 9/19頁 |
| 文件大小： | 406K |
| 代理商： | AD9281-EB |
AD9281
–9–
REV. E
The AD9281 can accommodate a variety of input spans be-
tween 1 V and 2 V. For spans of less than 1 V, expect a propor-
tionate degradation in SNR. Use of a 2 V span will provide the
best noise performance. 1 V spans will provide lower distortion
when using a 3 V analog supply. Users wishing to run with larger
full-scales are encouraged to use a 5 V analog supply (AVDD).
Single-Ended Inputs:
For single-ended input signals, the
signal is applied to one input pin and the other input pin is tied
to a midscale voltage. This midscale voltage defines the center
of the full-scale span for the input signal.
EXAMPLE: For a single-ended input range from 0 V to 1 V
applied to IINA, we would configure the converter for a 1 V
reference (see Figure 17) and apply 0.5 V to IINB.
I OR QREFT
I OR QREFB
IINA
IINB
VREF
REF SENSE
0.1
m
F
10
m
F
0.1
m
F
0.1
m
F
0.1
m
F
AD9281
0.1
m
F
10
m
F
10
m
F
MIDSCALE
VOLTAGE
= 0.5V (1V)
1V
0V
INPUT
5k
V
5k
V
Figure 17. Example Configuration for 0 V–1 V Single-
Ended Input Signal
Note that since the inputs are high impedance, this reference
level can easily be generated with an external resistive divider
with large resistance values (to minimize power dissipation). A
decoupling capacitor is recommended on this input to minimize
the high frequency noise-coupling onto this pin. Decoupling
should occur close to the ADC.
Differential Inputs
Use of differential input signals can provide greater flexibility in
input ranges and bias points, as well as offering improvements in
distortion performance, particularly for high frequency input
signals. Users with differential input signals will probably want
to take advantage of the differential input structure of the AD9281.
Performance is still very good for single-ended inputs. Convert-
ing a single-ended input to a differential signal for application to
the converter is probably only worth considering for very high
frequency input signals.
AC-Coupled Inputs
If the signal of interest has no dc component, ac coupling can be
easily used to define an optimum bias point. Figure 18 illustrates
one recommended configuration. The voltage chosen for the dc
bias point (in this case the 1 V reference) is applied to both
IINA and IINB pins through 1 k
resistors (R1 and R2). IINA
is coupled to the input signal through Capacitor C1, while IINB is
decoupled to ground through Capacitor C2.
0.1
m
F
10
m
F
0.1
m
F
0.1
m
F
ANALOG
INPUT
1.0
m
F
0.1
m
F
1k
V
1.5V
0.5V
I OR QREFT
I OR QREFB
IINA
IINB
VREF
AD9281
REFSENSE
Figure 18. Example Configuration for 0.5 V–1.5 V ac
Coupled Single-Ended Inputs
Transformer Coupled Inputs
Another option for input ac coupling is to use a transformer.
This not only provides dc rejection, but also allows truly differ-
ential drive of the AD9281’s analog inputs, which will provide
the optimal distortion performance. Figure 19 shows a recom-
mended transformer input drive configuration. Resistors R1 and
R2 define the termination impedance of the transformer cou-
pling. The center tap of the transformer secondary is tied to the
common-mode voltage, establishing the dc bias point for the
analog inputs.
0.1
m
F
10
m
F
0.1
m
F
0.1
m
F
COMMON
MODE
VOLTAGE
0.1
m
F
10
m
F
R1
R2
I OR QREFT
I OR QREFB
IINA
IINB
AD9281
QINB
QINA
REFSENSE
VREF
Figure 19. Example Configuration for Transformer
Coupled Inputs
Crosstalk:
The internal layout of the AD9281, as well as its
pinout, was configured to minimize the crosstalk between the
two input signals. Users wishing to minimize high frequency
crosstalk should take care to provide the best possible decoupling
for input pins (see Figure 20). R and C values will make a pole
dependant on antialiasing requirements. Decoupling is also
required on reference pins and power supplies (see Figure 21).
QINA
QINB
IINA
IINB
AD9281
Figure 20. Input Loading
DVDD
I OR QREFT
I OR QREFB
AVDD
0.1
m
F
10
m
F
0.1
m
F
10
m
F
AD9281
0.1
m
F
0.1
m
F
0.1
m
F
10
m
F
V ANALOG
V DIGITAL
Figure 21. Reference and Power Supply Decoupling
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